DS8500-KIT# Maxim Integrated Products, DS8500-KIT# Datasheet - Page 2

• Manufacturer Part Number: DS8500-KIT#
• Description: Power Management Modules & Development Tools DS8500 EVAL KIT DS8500 EVAL KIT
• Manufacturer: Maxim Integrated Products

Specifications of DS8500-KIT#

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This document must be used in conjunction with the fol-
lowing documents:
• DS8500 IC Data Sheet
• DS8500 EV Kit Data Sheet (this document)
• Application Note 4676: Introduction to the DS8500
The DS8500 evaluation kit (EV kit) contains all the nec-
essary receive and transmit filters that are required for
HART communication to a 4-20mA current loop in a pro-
cess control application. The EV board is prepopulated
with all the passives and the crystal required for proper
operation. Port pins provide easy monitoring of the sig-
nals associated with the device.
Power Supply: A typical 3.3V power supply needs to
be connected to V33 to power-up the IC along with the
board.
DS8500 Evaluation Kit
Table 1. Port Pin Description
2
Detailed Description of Hardware
PORT PIN #
HART Modem
______________________________________________________________________________________
P1.7, P1.8
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.1
P2.2
P2.3
P2.4
P2.5
PIN NAME
FSKOUT
OUT_B
RST_N
HOCD
FSKIN
HRXD
HTXD
HRTS
GND
GND
V33
V33
PIN TYPE
Output
Output
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Digital data output from DS8500 (DOUT)
Digital data input to DS8500(DIN)
Active-low reset signal to DS8500
Carrier-detect output from DS8500
Request-to-send signal to DS8500
3.3V power supply
Ground
3.3V power supply
HART input from 4-20mA current loop
HART output from DS8500
HART output by a unity gain amplifier, U2 (MAX4040EUK)
Ground
Clock Source: The 3.6864MHz crystal provides the
clock source to the DS8500 IC.
Receive Filters: The resistors and capacitors are popu-
lated on the board to separate the HART signal (FSK_IN)
from the noise of the 4-20mA current loop. For the
receive side a simple lowpass (10.1kHz) and a highpass
(481Hz) filter is sufficient to separate the HART signal.
These filters are realized by the following components:
• LoPass: 10.1kHz (R1, C3)
• HiPass: 481Hz (R2, R4, C7)
DC Bias Voltage: The resistor-divider formed by R2 and
R4 provides a DC bias voltage of V
FSK_IN receive signal.
Port Pins P1, P2: The port pins P1 (controller interface)
and P2 (HART interface) provide access to device.
DESCRIPTION
REF
/2 for the incoming