DS26514DK Maxim Integrated Products, DS26514DK Datasheet - Page 5

• Manufacturer Part Number: DS26514DK
• Description: Power Management Modules & Development Tools 4-Port T1-E1-J1 Tran Transceiver Demo Kit
• Manufacturer: Maxim Integrated Products

Specifications of DS26514DK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26514 4-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ......................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram........................................................................................................................... 19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 29
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 29
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 29
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 29
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 29
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................... 30
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................... 30
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................... 30
Figure 9-9. Backplane Clock Generation................................................................................................................... 31
Figure 9-10. Device Interrupt Information Flow Diagram........................................................................................... 35
Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz .................................................................................... 40
Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz .................................................................................... 41
Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................. 42
Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode............................................................................................... 46
Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode ................................................................... 46
Figure 9-16. CRC-4 Recalculate Method .................................................................................................................. 70
Figure 9-17. HDLC Message Receive Example........................................................................................................ 76
Figure 9-18. HDLC Message Transmit Example....................................................................................................... 78
Figure 9-19. Receive HDLC Example........................................................................................................................ 81
Figure 9-20. HDLC Message Transmit Example....................................................................................................... 83
Figure 9-21. Network Connection—Longitudinal Protection ..................................................................................... 86
Figure 9-22. T1/J1 Transmit Pulse Templates .......................................................................................................... 89
Figure 9-23. E1 Transmit Pulse Templates ............................................................................................................... 89
Figure 9-24. Receive LIU Termination Options ......................................................................................................... 91
Figure 9-25. Typical Monitor Application ................................................................................................................... 93
Figure 9-26. HPS Block Diagram............................................................................................................................... 95
Figure 9-27. Jitter Attenuation ................................................................................................................................... 96
Figure 9-28. Loopback Diagram ................................................................................................................................ 97
Figure 9-29. Analog Loopback................................................................................................................................... 97
Figure 9-30. Local Loopback ..................................................................................................................................... 98
Figure 9-31. Remote Loopback 2 .............................................................................................................................. 98
Figure 9-32. Dual Loopback ...................................................................................................................................... 99
Figure 11-1. T1 Receive-Side D4 Timing ................................................................................................................ 264
Figure 11-2. T1 Receive-Side ESF Timing.............................................................................................................. 264
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 265
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 265
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 266
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 267
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 268
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit.................................................................... 268
Figure 11-9. T1 Transmit-Side D4 Timing ............................................................................................................... 269
Figure 11-10. T1 Transmit-Side ESF Timing........................................................................................................... 269
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 270
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 270
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 271
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 272
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 273
Rev: 101608
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