71M6521BE-DB Maxim Integrated Products, 71M6521BE-DB Datasheet - Page 45

• Manufacturer Part Number: 71M6521BE-DB
• Description: Power Management Modules & Development Tools 71M6521BE DEMO BOARD M6521BE DEMO BOARD
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521BE-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

71M652X Software User’s Guide
Revision 1.7
FLAG interface
protocol
Reception of
calibration
parameters via
the serial interface
Count of
calibrations since
first cold reset.
Auto-calibration
Command Line
Interface (CLI)
Optical FLAG
Wired FLAG
Save registers
when sag occurs
Save to flash
memory
Save to and
restore from
EEPROM
Checksum
Feature
0.75KB
2.5KB
2.0KB
01.KB
1.2KB
1.2KB
0.9KB
0.7KB
3.5KB
0.2KB
Code
14KB
Size
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
N/opt
8KB
N
Y
Y
N
N
N
N
Y
Y
Y
16KB
N/opt
N/opt
N/opt
N/opt
N/opt
Y
Y
N
Y
Y
Y
TERIDIAN Proprietary
32KB
Feature
N/opt
N/opt
N/opt
N/opt
Y
Y
Y
Y
Y
Y
Y
Description
Implements the FLAG protocol stack (see the FLAG
specification). The FLAG protocol reads and writes
registers in the meter and responds to all ports.
Simple serial calibration system that supports reading
data and writing calibration values, including CE data,
MPU calibration and RTC settings. Meter operation is
not required when this feature is in use. Intel hex
records are used.
Counts calibrations. 0..254, 255 = “many”. The count
is protected by a checksum. The first cold reset is
detected by an invalid EEPROM. This is a tamper-
detection feature.
Internal automatic calibration, from command line
interface if available, or DIO state at start. Calibration
adjusts phase, as in the “fast calibration” described in
the DBUM.
Text-based commands give access to CE data, RAM,
IO registers. No help, profile or load features.
Versions without CLI can be controlled with
IOMERGE. The command line interface’s space is to
be counted as “unused” when calculating code space
margin.
Implementation of the physical FLAG layer on UART
1, 300 BAUD, using pulse output
Implementation of the physical FLAG layer on UART
0, 9600 BAUD,
Saves power and error registers on sag detection.
Compilation option to save calibration, error and
power register data to internal flash.
When a flash area is used-up, it is marked, and the
next one is used. When all areas are used up, an
error is recorded and write operations are inhibited.
Saves
register data to and from EEPROM.
When an EEPROM area is used-up, it is marked, and
the next one is used. When all areas are used up, an
error is recorded and write operations are inhibited.
Each revenue-affecting data area is protected by a
simple checksum
and restores
calibration, error and power
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