MAX17079EVKIT+ Maxim Integrated Products, MAX17079EVKIT+ Datasheet - Page 11

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MAX17079EVKIT+

Manufacturer Part Number
MAX17079EVKIT+
Description
Power Management Modules & Development Tools MAX17079 EVAL KIT MAX17079 EVAL KIT
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX17079EVKIT+

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 4. Startup Sequence
PROCESS: BiCMOS
The MAX17079 supply rail voltages should satisfy the
startup sequence shown in Figure 4. The supply rail
voltages should also satisfy the following conditions:
For proper operation, EN should be HIGH only after all
the supply rails are ON.
VLS ≥ VH1 ≥ (VH2, VL2, VCOM) ≥ VL1
______________________________________________________________________________________
4-Level or 2-Level Logic to High-Voltage
Level Shifter for TFT LCD TV Display
Chip Information
EN
Startup
VCC
VLS
VH1
VH2
VL2
VL1
VCOM
TIME
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
The load has a typical characteristic of large TFT LCD
panels. During state transitions, a built-in dead time
prevents shoot-through current. During dead time as
the output is not connected, the output can be affected
by the panel load. To avoid voltage spikes during the
deadline, 1nF to 4.7nF capacitors can be added at
each output.
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
PACKAGE TYPE
The MAX17079 has a backside pad to dissipate
heat. Do not route any trace around or under the
backside pad.
Ensure good decoupling of supply rails and put the
bypass capacitor for each power supply very close
to the pin.
Create an analog ground island (AGND) that
includes the AGND pin and the VCC bypass capaci-
tor to ground. Connect AGND to the backside pad
directly under the IC. Create a power ground plane
(DGND) that includes the DGND pin, the remaining
supply rails bypass capacitor grounds, and output
bypass capacitors, if used in the system. Connect
DGND to the backside pad directly under the IC.
Other than the backside connection, avoid connect-
ing AGND and DGND.
40 TQFN
PACKAGE CODE
Package Information
T4066+5
PCB Layout Guidelines
Load Characteristics
DOCUMENT NO.
21-0141
11

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