DS31404DK Maxim Integrated Products, DS31404DK Datasheet

DS31404DK

Manufacturer Part Number

DS31404DK

Description

Power Management Modules & Development Tools DS31404 Demonstratio 04 Demonstration Kit

Manufacturer

Maxim Integrated Products

Datasheet

1.DS31404DK.pdf (5 pages)

Specifications of DS31404DK

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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The DS31404 is a flexible, high-performance timing IC

for

synthesis applications. On each of its four input clocks

and eight output clocks, the device can accept or

generate nearly any frequency between 2kHz and

750MHz. The device offers two independent DPLLs to

serve two independent clock-generation paths.

The input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for

each of the two flexible, high-performance digital PLLs.

Each DPLL lock to the selected reference and provides

programmable bandwidth, very high resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLLs are followed by a clock

synthesis subsystem that has four fully programmable

digital frequency synthesis blocks, two high-speed low-

jitter APLLs, and eight output clocks, each with its own

32-bit divider and phase adjustment. The APLLs provide

fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31404 has all required

features and functions to serve as a central timing

function or as a line card timing IC. With a suitable

oscillator the DS31404 meets the requirements of

Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813,

and G.8262.

Frequency Conversion Applications in a Wide Variety of

Telecom Line Cards or Timing Cards with Any Mix of

+Denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device

errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

19-5710; Rev 0; 12/10

DS31404GN+

Equipment Types

SONET/SDH, Synchronous Ethernet and/or OTN

Ports in WAN Equipment Including MSPPs, Ethernet

Switches, Routers, DSLAMs, and Base Stations

diverse

PART

frequency

-40C to +85C

TEMP RANGE

Ordering Information

General Description

conversion

4-Input, 8-Output, Dual DPLL Timing IC

ABRIDGED DATA SHEET

Applications

and

PIN-PACKAGE

256 CSBGA

frequency

with Sub-ps Output Jitter



Four Input Clocks

Two High-Performance DPLLs

Four Digital Frequency Synthesizers

Two Output APLLs

Eight Output Clocks in Four Groups

General Features



Differential or CMOS/TTL Format

Any Frequency from 2kHz to 750MHz

Fractional Scaling for 64B/66B and FEC

Scaling (e.g., 64/66, 237/255, 238/255) or Any

Other Downscaling Requirement

Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Three 2/4/8kHz Frame Sync Inputs

Hitless Reference Switching on Loss of Input

Automatic or Manual Phase Build-Out

Holdover on Loss of All Inputs

Programmable Bandwidth, 0.5mHz to 400Hz

Each Can Slave to Either DPLL

Produce Any 2kHz Multiple Up to 77.76MHz

Per-DFS Clock Phase Adjust

Output Frequencies to 750MHz

High Resolution Fractional Scaling for FEC

and 64B/66B (e.g., 255/237, 255/238, 66/64)

or Any Other Scaling Requirement

Less than 1ps RMS Output Jitter

Simultaneously Produce Two Low-Jitter Rates

from the Same Reference (e.g., 622.08MHz

for SONET and 156.25MHz for 10GE)

Nearly Any Frequency from < 1Hz to 750MHz

Each Group Slaves to a DFS Clock, Any APLL

Clock, or Any Input Clock (Divided and Scaled)

Each Has a Differential Output (2 CML, 2

LVDS/LVPECL

32-Bit Frequency Divider Per Output

Two Sync Pulse Outputs: 8kHz and 2kHz

Suitable Line Card IC or Timing Card IC for

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

Accepts and Produces Nearly Any Frequency

Up to 750MHz Including 1Hz, 2kHz, 8kHz,

NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M,

125M, 156.25M, and Nx19.44M Up to 622.08M

Internal Compensation for Local Oscillator

Frequency Error

SPI™ Processor Interface

1.8V Operation with 3.3V I/O (5V Tolerant)

)

and Separate CMOS/TTL Output

Maxim Integrated Products 1

DS31404

Features

Related parts for DS31404DK

DS31404DK Summary of contents

Page 1

... Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M Internal Compensation for Local Oscillator Frequency Error SPI™ Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) Maxim Integrated Products 1 ...

Page 2

ABRIDGED DATA SHEET Application Example 19.44MHz, 38.88MHz, 25MHz, etc. system timing from master and slave timing cards line timing to master and slave timing cards 8kHz, 19.44MHz, 38.88MHz, 25MHz, etc. clock monitoring and selection, hitless switching, holdover, frequency conversion, fractional ...

Page 3

ABRIDGED DATA SHEET Block Diagram DS31404 SYNC1 SYNC2 SYNC3 Input Clock IC1 POS/NEG Block IC2 POS/NEG 8 Frequency Scaler, IC3 POS/NEG Activity Monitor, Freq. Monitor, IC4 POS/NEG Optional Inversion (per input clock) Clock status Selector JTRST JTMS JTAG JTCLK JTDI ...

Page 4

ABRIDGED DATA SHEET Detailed Features Input Clock Features  Four input clocks, differential or CMOS/TTL signal format  Input clocks can be any frequency from 2kHz up to 750MHz  Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, ...

Page 5

ABRIDGED DATA SHEET Output Clock Features  Eight output clock signals in four groups  Output clock groups OC1 and OC3 have a very high-speed differential output (current-mode logic, and a separate CMOS/TTL output (≤ 125MHz) ≤ 750MHz)  Output ...

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