DSDK2000 Maxim Integrated Products, DSDK2000 Datasheet - Page 14

• Manufacturer Part Number: DSDK2000
• Description: Power Management Modules & Development Tools HIGH PERFORMANCE DEM CE DEMO KIT PLATFORM
• Manufacturer: Maxim Integrated Products

Specifications of DSDK2000

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Slot LED registers control the LEDs on the daughter cards as follows:
The FPGA register holds the address of the FPGA on the board. This is reserved for future use. The FPGA is
unpopulated on most boards.
CS11. Chip select 11 is used by the EPLD. The current EPLD implementation has the registers defined in
Table 7. Chip Select 11 Mapping
UPDATE: Reset to 0. When 0, inhibits updating of the L2 cache.
TAG_CLR: Reset to 0. When 0, clears the L2 cache Tag.
FLUSH:
MISS_INH: Reset to 0. When 0, forces all L2 cache accesses to miss.
MPC8260 I/O Pin Mapping
The MPC8260 has 120 I/O pins that can be configured for special-purpose or general-purpose I/O. The DK2000
development platform takes advantage of as much of the I/O capability as possible.
pins are connected on the DK2000 board.
assignments.
ADDRESS OFFSET
00
01
10
11
0x00
0x01
Reset to 0. When 0, flushes the L2 cache.
LED is OFF
LED is ON and is RED
LED is ON and is GREEN
LED is OFF
UPDATE
BIT 0
TAG_CLR
BIT 1
Table 9
FLUSH
BIT 2
and
14 of 19
Table 10
MISS_INH
EPLD Version Number
BIT 3
add details on some of the special-purpose pin
BIT 4
BIT 5
Table 8
Unused
BIT 6
shows how the I/O
Table
BIT 7
7.