HSC-ADC-FPGA-9289 Analog Devices Inc, HSC-ADC-FPGA-9289 Datasheet - Page 5

• Manufacturer Part Number: HSC-ADC-FPGA-9289
• Description: EVAL BOARD FPGA FOR AD9289
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FPGA-9289

• Accessory Type: ADC Interface Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: AD9289 (Requires HSC-ADC-EVAL-DC)

THEORY OF OPERATION
The HSDB, featuring the Xilinx Virtex-II FPGA, accepts
four/eight ADC channels of LVDS serial data and the data
output and frame align clocks (DCO and FCO). The FPGA
then converts all of these signals from LVDS to single-ended
CMOS signals.
The HSDB can support 8-bit to 14-bit ADCs. The DCO signal
is used to clock the incoming data through 14 shift registers.
Seven of these registers are clocked on the rising edge of DCO,
and the other seven are clocked on the falling edge (DDR), as
shown in Figure 3. The ADC resolution is selectable using
Jumper Connection JP101 and Jumper Connection JP102.
Both the DCO and FCO are used inside the FPGA to set up
all necessary clock edges to take the parallel data from the shift
registers to the output of the FPGA. The DLL/Timing Reset
button (PB101) is used to set the data capture timing to the
default setting (see Table 4).
Once the parallel data has been transferred completely to the
FCO clock domain, the data is multiplexed for use with the
2-channel FIFO board (HSC-ADC-EVALA/B-DC). ADC
LVDS OUTPUTS
WITH SERIAL
OCTAL ADC
FCO
DCO
CHA
CHB
CHC
CHD
CHE
CHF
CHG
CHH
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
LVDS – CMOS
JP, PB100, PB101
Figure 3. Internal FPGA Functional Block Diagram
SHIFT FALLING
SHIFT FALLING
SHIFT FALLING
SHIFT FALLING
SHIFT FALLING
SHIFT FALLING
SHIFT FALLING
SHIFT FALLING
SHIFT RISING
SHIFT RISING
SHIFT RISING
SHIFT RISING
SHIFT RISING
SHIFT RISING
SHIFT RISING
SHIFT RISING
Rev. C | Page 5 of 20
JP101, JP102
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
ASSEMBLE
ASSEMBLE
ASSEMBLE
ASSEMBLE
ASSEMBLE
ASSEMBLE
ASSEMBLE
ASSEMBLE
Channel A and Channel B are selected using the JP104 jumper
connection. Channel C and Channel D are selected using the
JP103 jumper connection. Data clock outputs (CLK_AB and
CLK_CD) are also provided to clock the FIFO board.
CODE DESCRIPTION
The FPGA on the HSDB comes with Verilog code preinstalled
and tested. It is designed to help evaluate the performance of an
Analog Devices quad/octal ADC quickly and easily by
providing the user with familiar CMOS logic-level outputs.
MANUAL INSTALLATION AND CUSTOMIZATION
Users can manually customize or update the necessary code
through a JTAG connector provided on the deserialization
board, as shown in Figure 2. However, Analog Devices provides
no guarantee of performance if the code is customized.
A Zip file containing all of the necessary default configuration
files to implement manual changes or to add custom module
blocks for further computation is at www.analog.com/FIFO.
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
JP103
JP104
JP105
JP106
n
n
n
n
n
n
n
n
MUX
MUX
n
n
DATA OUT ABCD
DATA OUT EFGH
CLK_ABCD
CLK_EFGH
HSC-ADC-FPGA