LFE2-50E-D-EV Lattice, LFE2-50E-D-EV Datasheet - Page 33
LFE2-50E-D-EV
Manufacturer Part Number
LFE2-50E-D-EV
Description
MCU, MPU & DSP Development Tools LS Mico32/DSP Dev Br Brd for LS ECP2
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-50E-D-EV
Processor To Be Evaluated
LatticeECP2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 2-28. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-28.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
DDRCLKPOL*
*Signals are available on left/right/bottom edges only.
** Selected blocks.
DQSXFER*
QNEG0*
QNEG1*
ONEG2*
QPOS0*
QPOS1*
OPOS2*
ONEG0
OPOS0
ONEG1
INDD
OPOS1
INCK**
ECLK1
ECLK2
IPOS0
IPOS1
GSRN
INFF
CLK
LSR
CE
TD
Control
Muxes
CLK1
CLK0
CEO
GSR
LSR
CEI
2-30
PIOA
Register
Register
Register
Tristate
Output
Block
Block
Block
Input
PIOB
IOLD0
IOLT0
DI
LatticeECP2/M Family Data Sheet
Buffer
sysIO
PADB
PADA
“C”
“T”
Architecture
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