Core429-DEV-KIT-FPL Actel, Core429-DEV-KIT-FPL Datasheet - Page 18
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Core429-DEV-KIT-FPL
Manufacturer Part Number
Core429-DEV-KIT-FPL
Description
MCU, MPU & DSP Development Tools ARINC 429 Bus Interface
Manufacturer
Actel
Datasheet
1.CORE429-DEV-KIT-FPL.pdf
(22 pages)
Specifications of Core429-DEV-KIT-FPL
Processor To Be Evaluated
ProASIC Plus
Interface Type
RS-232
Line Drivers
Core429 needs ARINC 429 line drivers to drive the ARINC 429 data bus. Core429 is designed to directly interface to
common ARINC 429 line drivers, such as the HOLT HI-8382/HI-8383, DDC DD-03182 or Device Engineering DEI1070.
Figure 14
Figure 14 •
Line Receivers
Core429 needs ARINC 429 line receivers to receive the
ARINC 429 data bus. Core429 is designed to directly
interface to common ARINC 429 line receivers, such as
the HOLT HI-8588 or Device Engineering DEI3283. When
using ProASIC
level translators are required to connect the 5 V output
levels of the Core429 line receivers to the 3.3 V input
levels of the FPGA.
Figure 15 on page 19
from Core429 to the line receivers.
Loopback Interface
If the loopback bit in the transmit control register is
enabled, the transmit outputs will be connected to the
receive inputs. If there are equal numbers of transmit
and receive channels, each transmit channel output is
connected to the corresponding receive channel input.
As an example, transmit channel 0 output is connected
to receive channel 0 input.
If there are more receive channels than transmit
channels, then the extra receive channels are connected
to transmit channel 0. As an example, if we have two
transmit channels (0 and 1) and four receive channels (0,
1, 2, and 3) then the connections are made as follows:
1 8
ARINC 429 Bus Interface
• Connect transmit channel 0 output to receive
• Connect transmit channel 1 output to receive
channel 0 inputs.
channel 1 input.
shows the connections required from Core429 to the line drivers.
Core429 Line Driver and Line Receiver Interface
PLUS
, RTAX-S, or Axcelerator FPGA families,
shows the connections required
Interface
CPU
CoreARINC429
Rx I/F
Tx I/F
v5.0
Development System
A complete ARINC 429 development system is also
available, Actel part number "Core429-DEV-KIT". The
development system uses an external terminal (PC) using
a serial UART link to control Core429 with four Rx and
four Tx channels implemented in a single ProASIC
APA600 FPGA.
The loopback interface logic allows the ARINC core to
operate with the loopback mode. The development kit
(Figure 15 on page
line receivers.
On power-up, Core8051 will read the message from the
ADC, which could be the aircraft fuel level or flap
position, for example, and transmits over the transmit
channel. The message will be transmitted to the receiver
through the loopback interface. Then the message will
be retrieved by Core8051 from the receiver and
displayed on the LCD display.
Another way is to transmit the ADC message over the
transmit channel through the line drivers to another
system similar to the one described above. The message
will go through the receive channel of the second system
and can be displayed on the LCD display.
• Connect transmit channel 0 output to receive
• Connect transmit channel 0 output to receive
Line Driver
Line Receiver
channel 2 input.
channel 3 input.
TxHi
TxLo
RxHi
RxLo
19) includes ARINC line drivers and
PLUS