LS-XP10-BASE-PC-N Lattice, LS-XP10-BASE-PC-N Datasheet
LS-XP10-BASE-PC-N
Specifications of LS-XP10-BASE-PC-N
Related parts for LS-XP10-BASE-PC-N
LS-XP10-BASE-PC-N Summary of contents
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... Commercial and 7.5ns t PD — 182MHz f CNT ◆ 512 macrocells 768 registers ◆ 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages ◆ Flexible architecture for a wide range of design styles — D/T registers and latches — Synchronous or asynchronous mode — ...
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... CNT t (ns) 4.0 4.0 COS t (ns) 3.0 3.5 SS Static Power (mA) 20 25/52 JTAG Compliant Yes Yes PCI Compliant Yes Yes 5 V Devices Feature M4A5-32 M4A5-64 Macrocells 32 64 User I/O options (ns) 5.0 5 (MHz) 182 167 CNT t (ns) 4.0 4.0 COS t (ns) 3.0 3 ...
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... The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5- xxx) and 3.3-V (M4A3-xxx) operation. ...
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... Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive 3 ...
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... I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently ...
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... The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate with each other with consistent, predictable delays ...
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... M4A3-512 Logic Allocator Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number of unused— ...
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Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32) Output Macrocell Output Macrocell ...
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... In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell. Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available. ...
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Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset ...
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The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that ...
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Configuration D-type Register T-type Register D-type Latch Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, ...
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A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. ...
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... Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells ...
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... M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M0, M1, M10, M11, M12, M13, M14, M15 M0, M1, M2, M3, M12, M13, M14, M15 M0, M1, M2, M3, M4, M5, M14, M15 Routable to I/O Cells I/O1 I/O2 I/O3 I/O4 I/O5 ...
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... I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15 Routable to I/O Cells I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15 ...
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... I/O pin and compared with the previous stored value. Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells. It powers logic low. ...
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... The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix. Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell ...
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... PAL Block Clock Generation Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals ...
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... A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer using external feedback ...
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... IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification ...
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... Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. HOT SOCKETING ispMACH 4A devices are well-suited for those applications that require hot socketing capability ...
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INPUT SWITCH MATRIX Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio M4A(3, 5)-64/32 M4A3-64/64 M4(3, 5)-192/96 M4A(3, 5)-96/48 M4(3, 5)-256/128 CLOCK M4A(3, 5)-128/64 GENERATOR ...
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INPUT 32 SWITCH MATRIX Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32) 24 M4A3-256/160 M4A3-64/64 M4A3-256/192 CLOCK GENERATOR MACROCELL ...
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INPUT 32 SWITCH MATRIX Figure 18. PAL Block for M4A (3,5)-32/32 CLK0/I0 CLK0/I1 CLOCK GENERATOR MACROCELL MACROCELL MACROCELL MACROCELL O3 M3 ...
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... Logic Allocator 16 33 Central Switch Matrix AND Logic Array and Logic Allocator 8 2 Macrocells Output Switch Matrix 8 I/O Cells 8 I/O16–I/O23 Block B ispMACH 4A Family I/O0–I/O7 8 I/O Cells 8 Output Switch Matrix Macrocells Macrocells Output Switch Matrix 8 I/O Cells 8 I/O24–I/O31 17466H-019 ...
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... X 90 AND Logic Array AND Logic Array 2 and Logic Allocator and Logic Allocator 16 Macrocells Output Switch Matrix 4 8 I/O Cells 8 I/O8–I/O15 Block B ispMACH 4A Family Block D I/O24–I/O31 8 I/O Cells 8 Output Switch Matrix Macrocells Macrocells Output Switch Matrix 8 I/O Cells 8 I/O16–I/O23 ...
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... Output Switch Matrix Macrocells Macrocells AND Logic Array and Logic Allocator 33 33 Central Switch Matrix AND Logic Array 4 and Logic Allocator 16 16 Macrocells Macrocells Output Switch Output Switch Matrix 16 16 I/O Cells I/O Cells 16 16 Block B Block C ispMACH 4A Family Matrix Matrix 17466H-020A ...
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BLOCK DIAGRAM – M4A(3,5)-96/48 Clock Generator Clock Generator Clock Generator I2, I3, I6, I7 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 ispMACH ...
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BLOCK DIAGRAM – M4A(3,5)-128/64 Clock Generator Clock Generator Clock Generator Clock Generator I2, I5 Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE Input Switch Input Switch Matrix Matrix OE OE Input Switch ...
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... AND Logic Array 4 4 and Logic Allocator and Logic Allocator 16 16 Macrocells Macrocells Output Switch Output Switch Matrix Matrix I/O Cells I/O Cells I0—I15 I/O24—I/O31 I/O32—I/O39 Block F Block G ispMACH 4A Family Block K I/O64—I/O71 8 I/O Cells 8 4 Output Switch Matrix ...
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... AND Logic Array 4 4 and Logic Allocator and Logic Allocator 16 16 Macrocells Macrocells Output Switch 8 8 Output Switch Matrix Matrix I/O Cells I/O Cells I0–I13 I/O56–I/O63 I/O64–I/O71 Block H Block I ispMACH 4A Family Block O I/O112–I/O119 8 I/O Cells 8 4 Output Switch Matrix ...
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... AND Logic Array AND Logic Array 4 4 and Logic Allocator and Logic Allocator 16 Macrocells Output Switch 16 16 Output Switch Matrix I/O Cells 16 Block H ispMACH 4A Family Block P Block I/O Cells I/O Cells Output Switch Matrix Matrix Macrocells Macrocells AND Logic Array and Logic Allocator ...
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... AND Logic Array AND Logic Array 4 4 and Logic Allocator and Logic Allocator 16 16 Macrocells Macrocells Output Switch Output Switch Matrix Matrix I/O Cells I/O Cells 8 8 Block L Block M ispMACH 4A Family Block GX 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array ...
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... AND Logic Array AND Logic Array 4 4 and Logic Allocator and Logic Allocator 16 16 Macrocells Macrocells Output Switch Output Switch Matrix Matrix I/O Cells I/O Cells 8 8 Block P Block AX ispMACH 4A Family Block OX 8 I/O Cells 8 4 Output Switch Matrix Macrocells AND Logic Array ...
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ABSOLUTE MAXIMUM RATINGS M4A5 Storage Temperature -65°C to +150°C Ambient Temperature with Power Applied ...
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... Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Notes: 1. See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. ...
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TIMING PARAMETERS OVER OPERATING RANGES Combinatorial Delay: Internal combinatorial propagation t PDi delay t Combinatorial propagation delay PD Registered Delays: Synchronous clock setup time, D-type t SS register Synchronous clock setup time, T-type t SST register Asynchronous clock ...
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... Asynchronous reset and preset register t SRR recovery time t Asynchronous reset or preset width SRW Clock/LE Width: t Global clock width low WLS t Global clock width high WHS t Product term clock width low WLA t Product term clock width high WHA Global gate width low (for low ...
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... D-type, Min of CNT f MAXS 1/( 1/( WLS WHS SS COSi Internal feedback (f ), T-type, Min of CNT 1/( 1/( WLS WHS SST COSi 2 No feedback , Min of 1/( WLS WHS 1/( 1/( SST HS External feedback, D-type, Min 1/( WLA WHA SA COA External feedback, T-type, Min of 1/(t WLA + 1/( WHA SAT COA ...
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... Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. ...
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PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View M4A(3,5)-64 I/O7 TDI CLK0/I0 M4A(3,5)-32/32 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4A(3,5)-64/32 PIN DESIGNATIONS CLK/I ...
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TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View M4A(3,5)-64 I/O7 TDI M4A(3,5)-32/32 CLK0/I0 GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4A(3,5)-64/32 PIN DESIGNATIONS CLK/I ...
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TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View M4A(3,5)-64 I/O7 TDI CLK0/I0 M4A(3,5)-32/32 NC GND TCK I/O9 A10 B2 I/O10 A11 B3 I/O11 M4A(3,5)-64/32 PIN DESIGNATIONS ...
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TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48) Top View NC 1 TDI I/O10 9 B3 I/O11 10 I0/CLK0 GND 13 ...
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PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64) Top View GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 ...
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TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64) Top View GND 1 TDI I/ I/ I/O10 I/O11 I/O12 7 B2 A11 I/O13 8 B1 A13 I/O14 ...
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CONNECTION DIAGRAM (M4A3-128/64) Bottom View 10 9 I/O63 GND A H7 TRST GND B I/O53 TDO C G5 I/O50 I/O55 I/O49 E CLK3/ GND VCC I/O41 CLK2/ I/O44 I/O45 H F4 ...
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TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96) Top View GND 1 TDI ...
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FPBGA CONNECTION DIAGRAM (M4A3-192/96) Bottom View I/O72 I/O76 A GND L7 L3 I/O73 I/O77 I/O79 B GND L6 L2 I/O74 C GND TDO L5 I/O67 I/O69 I/O71 I/O75 I/O64 I/O66 I/O70 E ...
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PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 AND M4A3-256/160) Top View GND 1 GND TDI 2 TDI C7 I/O16 3 C15 I/O20 C6 I/O17 4 C14 I/O21 C5 I/O18 5 I/O22 C13 C4 I/O19 6 C12 I/O23 C3 I/O20 7 C11 I/O24 ...
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PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160) Top View GND GND 1 TDI TDI 2 F7 I/O18 C7 I/O18 3 F6 I/O19 C6 I/O19 4 F5 I/O20 C5 I/O20 5 F4 I/O21 C4 I/O21 6 F3 I/O22 C3 I/O22 7 ...
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BGA CONNECTION DIAGRAM (M4A3-256/128) Bottom View I/O108 I/O105 A GND N/C GND GND N4 N1 I/O113 I/O109 I/O106 I/O103 B GND N I/O116 I/O111 I/O107 TRST C N/C VCC ...
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CONNECTION DIAGRAM (M4A3-256/192) Bottom View I/O167 I/O181 I/O180 I/O177 I/O174 A N15 O13 O12 O9 O6 I/O165 I/O166 I/O182 I/O179 I/O175 B N13 N14 O14 O11 O7 I/O163 I/O164 I/O183 I/O178 C NC ...
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BGA CONNECTION DIAGRAM - (M4A3-384/192) Bottom View I/O11 I/O44 I/O58 A GND GND GND FX7 FX6 CX6 I/O12 I/O28 I/O45 I/O59 I/O64 B GND GX7 FX5 FX3 CX7 CX5 I/O0 I/O13 I/O46 I/O60 ...
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CONNECTION DIAGRAM (M4A3-256/128) Bottom View I/O117 I/O116 I/O113 I/O126 TRST I/O110 I/O111 I/O118 I/O115 I/O127 I/O108 I/O109 I/O119 I/O114 ...
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CONNECTION DIAGRAM (M4A3-384/192) Bottom View I/O175 I/O181 I/O180 I/O177 A FX7 GX5 GX4 GX1 I/O173 I/O174 I/O182 I/O179 B FX5 FX6 GX6 GX3 I/O171 I/O172 I/O183 C N/C FX3 FX4 GX7 I/O150 I/O151 D ...
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CONNECTION DIAGRAM (M4A3-512/192) Bottom View I/O159 I/O181 I/O180 I/O177 I/O174 A KX7 OX5 OX4 OX1 I/O157 I/O158 I/O182 I/O179 I/O175 B KX5 KX6 OX6 OX3 I/O155 I/O156 I/O183 I/O178 C N/C KX3 KX4 OX7 ...
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CONNECTION DIAGRAM (M4A3-512/256) Bottom View GND I/O243 I/O240 I/O241 I/O236 I/O231 I/O228 A OX3 OX0 OX1 NX4 MX7 MX4 GND I/O245 I/O242 I/O238 I/O234 I/O232 B N/C OX5 OX2 NX6 NX2 NX0 ...
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... Macrocells Macrocells 256 = 256 Macrocells Macrocells 384 = 384 Macrocells 128 = 128 Macrocells 512 = 512 Macrocells I/Os / I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP / I/Os in 100-pin TQFP / I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA / I/Os in 144-pin TQFP or 144-ball fpBGA /128 ...
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... Most ispMACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4A3-256/128-7YC-10YI Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. ...
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... Revised M4A3-256/160 208-pin PQFP connection diagram. © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...