Si5338-PROG-EVB Silicon Laboratories Inc, Si5338-PROG-EVB Datasheet - Page 8
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Si5338-PROG-EVB
Manufacturer Part Number
Si5338-PROG-EVB
Description
Programmers & Debuggers Si5338/4/0 field programming kit
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5338-EVB.pdf
(42 pages)
Specifications of Si5338-PROG-EVB
Positions/sockets
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Si5338
Table 6. Input and Output Clock Characteristics
(V
8
Parameter
Input Clock (AC Coupled Differential Input Clocks on Pins IN1/2, IN5/6)
Frequency
Differential Voltage
Swing
Rise/Fall Time
Duty Cycle
Input Impedance
Input Capacitance
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency
Input Voltage
Input Voltage Swing
Rise/Fall Time
Rise/Fall Time
Duty Cycle
Input Capacitance
Output Clocks (Differential)
Frequency
LVPECL Output Volt-
age
LVDS Output Voltage
(2.5/3.3 V)
LVDS Output Volt-
age (1.8 V)
Notes:
DD
1. For best jitter performance, keep the midpoint differential input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the mid point input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6. See "3.3. Synthesis
5. Includes effect of internal series 22 resistor.
6. Use an external 100 resistor to provide load termination for a differential clock. See Figure 3.
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
Stages" on page 17
4
1
2,3
6
Symbol
V
V
V
f
t
t
t
V
V
V
V
DC
R
C
DC
C
OUT
SEPP
SEPP
SEPP
R
R
R
f
f
V
OC
OC
OC
IN
IN
PP
/t
/t
/t
IN
IN
IN
I
F
F
F
peak-to-peak single-
peak-to-peak single-
peak-to-peak single-
LVPECL, LVDS
common mode
common mode
common mode
Test Condition
710 MHz input
ended swing
ended swing
ended swing
20%–80%
10%–90%
20%–80%
< 1 ns tr/tf
< 4 ns tr/tf
200 MHz
CMOS
HCSL
A
Rev. 1.0
= –40 to 85 °C)
1.125
–0.1
0.16
0.16
0.55
0.25
0.25
367
550
Min
0.8
0.8
0.4
40
10
40
—
—
—
—
—
—
5
5
6
V
1.45 V
0.875
0.35
0.35
DDO
Typ
3.5
2.0
0.8
1.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–
VDD+10%
473.33
1.275
3.73
0.96
0.45
0.95
0.45
Max
200
350
710
250
710
1.0
2.3
2.4
60
—
—
60
—
—
4
Units
MHz
MHz
MHz
MHz
MHz
MHz
Vpp
V
V
V
V
k
ns
pF
ns
ns
pF
%
%
V
V
V
V
PP
PP
PP
PP