ST7MDT5-EPB/US STMicroelectronics, ST7MDT5-EPB/US Datasheet
ST7MDT5-EPB/US
Specifications of ST7MDT5-EPB/US
Related parts for ST7MDT5-EPB/US
ST7MDT5-EPB/US Summary of contents
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UP TO 64K ROM/OTP/EPROM AND RAM Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes Internal Memory: – EPROM/OTP/ROM 24/32/48/64K bytes – ROMless version available – RAM 768/1K/1.5K/2K bytes Maximum External Memory: ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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WAIT: External Memory Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI- 144 9.6.1 Introduction . . . . . . . . . . . . . . . . . . . ...
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ST90158 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST90158 and ST90135 microcontrollers are developed and manufactured by STMicroelectron- ics using a proprietary n-well CMOS process. Their performance derives from the use of a flexi- ble 256-register programming model ...
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Multifunction Timers (MFT) Each multifunction timer has a 16-bit Up/Down counter supported by two 16-bit Compare regis- ters and two 16-bit input capture registers. Timing resolution can be programmed using an 8-bit pres- caler. Multibyte transfers between the peripheral ...
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ST90158 - GENERAL DESCRIPTION Figure 1. ST90158 Block Diagram EPROM/ ROM/OTP Kbytes RAM Kbytes AS WAIT 256 bytes NMI Register File R/W DS 8/16 bits CPU Interrupt Management INT0-7 ST9 CORE OSCIN OSCOUT RESET ...
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Figure 2. ST90135 Block Diagram ROM Kbytes RAM Kbyte AS WAIT 256 bytes NMI Register File R/W DS 8/16 bits CPU Interrupt Management INT0-7 ST9 CORE OSCIN OSCOUT RESET RCCU INTCLK CKAF WDIN WDOUT ...
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ST90158 - GENERAL DESCRIPTION 1.2 PIN DESCRIPTION RESET: Reset (input, active low). The ST9 is ini- tialised by the Reset signal. With the deactivation of RESET, program execution begins from the memory location pointed to by the vector con- tained ...
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PIN DESCRIPTION (Cont’d) Figure 3. 80-Pin TQFP Pin-out 80 AD6/P0 AD7/P0 P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 WDOUT/INT0/P4.4 INT4/P4.5 T0OUTB/INT5/P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 20 P2.4 21 ST90158 - GENERAL DESCRIPTION ...
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ST90158 - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) Figure 4. 80-Pin PQFP Pin-Out AD4/P0.4 AD5/P0.5 AD6/P0 AD7/P0 P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 INT0/WDOUT/P4.4 INT4/P4.5 INT5/T0OUTB/P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 ...
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I/O PORT PINS All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels (except where Schmitt Trig- ger is present). Each bit can be programmed indi- vidually (Refer ...
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ST90158 - GENERAL DESCRIPTION I/O PORT PINS (Cont’d) How to Configure the I/O ports To configure the I/O ports, use the information in Table 1, Table 2 and the Port Bit Configuration Ta- ble (Table 19) in the I/O Ports ...
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Pin No. Port General Purpose I/O Name P1 A10 P1 A11 P1 A12 P1 A13 P1 A14 P1 A15 ...
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ST90158 - GENERAL DESCRIPTION Pin No. Port General Purpose I/O Name R P7.3 ...
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Pin No. Port General Purpose I/O Name P9 S1OUT P9 P9 All ports useable for general pur- P9.4 pose I/O (input output or bidirec- tional) P9 S0IN P9 ...
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ST90158 - DEVICE ARCHITECTURE 2 DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9 Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean ...
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MEMORY SPACES (Cont’d) Figure 6. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure 8. Addressing the Register ...
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ST90158 - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h ...
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SYSTEM REGISTERS The System registers are listed in are used to perform all the important system set- tings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description of the PORT[5:0] ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the ...
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SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 Bits 7:3 = RG[4:0]: Register Group number. These bits contain the ...
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SYSTEM REGISTERS (Cont’d) Figure 9. Pointing to a single group of 16 registers REGISTER BLOCK GROUP NUMBER REGISTER FILE r15 3 ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always ...
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SYSTEM REGISTERS (Cont’d) state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise re- duction when only internal Memory is used. If Port 1 and/or 2 are ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP15 USP14 USP13 USP12 USP11 USP10 USP9 USP8 USER STACK POINTER LOW REGISTER (USPLR) R237 - ...
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MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ...
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ST90158 - DEVICE ARCHITECTURE 2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers ...
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ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical ...
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ST90158 - DEVICE ARCHITECTURE ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three ...
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MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0_7 DPR0_6 DPR0_5 DPR0_4 DPR0_3 DPR0_2 DPR0_1 DPR0_0 Bits 7:0 = DPR0_[7:0]: ...
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ST90158 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has ...
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MMU REGISTERS (Cont’d) Figure 16. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 9 ST90158 - DEVICE ARCHITECTURE 4M bytes 16K 16K 16K 64K 64K 16K 64K 3FFFFFh 294000h 240000h 23FFFFh 20C000h 200000h 1FFFFFh 040000h 03FFFFh 030000h ...
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ST90158 - DEVICE ARCHITECTURE 2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, ...
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... STMicroelectronics. 3.2 EPROM PROGRAMMING The 65536 bytes of EPROM memory of the ST90E158 may be programmed by using the EPROM Programming Boards (EPB) available from STMicroelectronics or gang programmers available from third party. EPROM Erasing The EPROM of the windowed package of the ST90E158 may be erased by exposure to Ultra-Vi- olet light ...
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ST90158 - REGISTER AND MEMORY MAP Figure 17. Interrupt Vector Table REGISTER FILE F PAGE REGISTERS INT. VECTOR REGISTER R240 R239 38/199 9 PROGRAM MEMORY USER ISR USER DIVIDE-BY-ZERO ISR USER MAIN PROGRAM USER TOP LEVEL ISR 0000FFh ODD LO ...
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MEMORY MAP Figure 18. Memory Map 20FFFFh Internal RAM 768 bytes 20FD00h 1 Kbytes 20FC00h 1.5 Kbytes 20FA00h 2 Kbytes 20F800h 00FFFFh 64 Kbytes 00BFFFh 48 Kbytes 007FFFh 32 Kbytes 00FFFFh Internal ROM 24 Kbytes Note: The total amount ...
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ST90158 - REGISTER AND MEMORY MAP 3.4 ST90158/135 REGISTER MAP The following pages contain a list of ST90158/135 registers, grouped by peripheral or function. Table 6. Common Registers Function or Peripheral SCI, MFT ADC SPI, WDT, STIM I/O PORTS EXTERNAL ...
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Table 7. Group F Pages Resources available on the ST90158/ST90135 devices: Register R255 Res. R254 PORT SPI 7 R253 Res. R252 WCR R251 R250 PORT WDT 6 PORT R249 2 R248 MFT1 R247 Res. Res. R246 PORT ...
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ST90158 - REGISTER AND MEMORY MAP Table 8. Detailed Register Map Page Reg. Block No. (Decimal) R230 R231 R232 R233 R234 Core R235 R236 N/A R237 R238 R239 R224 I/O R225 Port R226 5:4,2:0 R228 R229 MR R241 R242 R243 ...
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Page Reg. Block No. (Decimal) R240 I/O Port R241 4 R242 R244 I/O Port R245 5 R246 R248 3 I/O R249 Port R250 6 R251 R252 I/O R253 Port R254 7 R255 9 ST90158 - REGISTER AND MEMORY MAP Register ...
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ST90158 - REGISTER AND MEMORY MAP Page Reg. Block No. (Decimal) R240 R241 R242 R243 R244 R245 R246 R247 8 R248 R249 MFT1 R250 R251 R252 R253 R254 R255 R244 R245 R246 R247 9 MFT0,1 R248 R240 R241 R242 R243 ...
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Page Reg. Block No. (Decimal) R240 R241 11 STIM R242 R243 R240 REG0HR1 R241 REG0LR1 R242 REG1HR1 R243 REG1LR1 R244 CMP0HR1 R245 CMP0LR1 R246 CMP1HR1 R247 CMP1LR1 12 R248 R249 MFT3 R250 R251 R252 R253 R254 R255 R244 R245 13 ...
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ST90158 - REGISTER AND MEMORY MAP Page Reg. Block No. (Decimal) R240 R241 R242 R243 R244 R245 R246 R247 24 SCI0 R248 R248 R249 R250 R251 R252 R253 R254 R255 R240 R241 R242 R243 R244 R245 R246 R247 SCI1 25 ...
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Page Reg. Block No. (Decimal) R240 55 RCCU R242 CLK_FLAG R246 R240 R241 R242 R243 R244 R245 R246 R247 63 AD0 R248 R249 R250 R251 R252 R253 R254 R255 (*) Not present on ST90135. Note: xx denotes a byte with ...
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ST90158 - INTERRUPTS 4 INTERRUPTS 4.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event ...
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Segment Paging Routines The ENCSR bit in the EMR2 register can be used to select whether the CSR is saved or not when an interrupt occurs. For a description of the EMR2 register, refer to the External Memory Interface ...
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ST90158 - INTERRUPTS with the highest position in the chain, as shown in Figure 9 Table 9. Daisy Chain Priority Highest Position INTA0 INTA1 INTB0 INTB1 INTC0 INTC1 INTD0 INTD1 TIMER0 SCI0 SCI1 A/D TIMER3 Lowest Position TIMER1 4.4.4 Dynamic ...
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ARBITRATION MODES (Cont’d) Examples In the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. Figure 21. Simple Example of a Sequence of Interrupt Requests ...
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ST90158 - INTERRUPTS ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, 22), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for requests ...
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ARBITRATION MODES (Cont’d) 4.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to Con- current mode, ...
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ST90158 - INTERRUPTS ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – ...
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EXTERNAL INTERRUPTS The standard ST9 core contains 8 external inter- rupts sources grouped into four pairs. Table 10. External Interrupt Channel Grouping External Interrupt INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 Each source has a trigger control bit ...
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ST90158 - INTERRUPTS EXTERNAL INTERRUPTS (Cont’d) Figure 26. External Interrupts Control Bits and Vectors n Watchdog/Timer End of count TEA0 INT 0 pin INT 1 pin SPEN,BMS TEB0 SPI Interrupt INT 2 pin INT 3 pin TEC0 STD Timer INT ...
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TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high ...
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ST90158 - INTERRUPTS 4.9 INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK ...
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INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-bit ...
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ST90158 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit ...
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INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h TLTEV TLIS IAOS EWEN Bit 7:4 = V[7:4]: Most significant nibble of External Interrupt Vector . ...
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ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 5 ON-CHIP DIRECT MEMORY ACCESS (DMA) 5.1 INTRODUCTION The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is ...
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DMA TRANSACTIONS The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations: – A load from/to the peripheral data ...
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ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared. To select between using the ISR or the DMASR reg- ister to extend the ...
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DMA TRANSACTIONS (Cont’d) 5.4 DMA CYCLE TIME The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their priority al- lows it. A DMA transfer ...
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ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 5.6 DMA REGISTERS As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown ...
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RESET AND CLOCK CONTROL UNIT (RCCU) 6.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) com- prises two distinct sections: – the Clock Control Unit, which generates and manages the internal clock signals. – the Reset/Stop Manager, which detects ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) 6.3 CLOCK MANAGEMENT The various programmable features and operating modes of the CCU are handled by four registers: – MODER (Mode Register) This is a System Register (R235, Group E). The input ...
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CLOCK MANAGEMENT (Cont’d) 6.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condi- tion), CLOCK2, is equal to CLOCK1 divided by two; ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 6.3.4 Low Power Modes The user can select an automatic slowdown of clock frequency during Wait for Interrupt opera- tion, thus idling in low power mode while waiting for ...
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Figure 34. Example of Low Power mode programming in WFI using CK_AF external clock PROGRAM FLOW Begin MX(1:0) DX2-0 WAIT CSU_CKSEL WFI_CKSEL XTSTOP LPOWFI User’s Program WFI instruction WFI status Interrupt Interrupt Routine XTSTOP WAIT CKAF_SEL WAIT CSU_CKSEL User’s Program ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 35. Example of Low Power mode programming in WFI using CLOCK2/16 PROGRAM FLOW Begin MX(1:0) DX2-0 WAIT CSU_CKSEL LPOWFI User’s Program WFI instruction WFI status Interrupt Interrupt Routine WAIT CSU_CKSEL User’s ...
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CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 *Note: This register contains bits which relate to other functions; these are described in the chapter dealing ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0100 10x0 after a Watchdog Reset Reset Value: 0010 10x0 after a Software Reset Reset Value: 0000 ...
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CLOCK CONTROL REGISTERS (Cont’d) PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: xx00 x111 MX1 MX0 - Bit 5:4 = MX[1:0]: PLL Multiplication Factor . Refer to Table 13 for multiplier settings. WARNING: ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) 6.5 OSCILLATOR CHARACTERISTICS The on-chip oscillator circuit uses an inverting gate circuit with tri-state output. Notes recommended to place the quartz or crystal as close as possible to the ST9 ...
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OSCILLATOR CHARACTERISTICS (Cont’d) CERAMIC RESONATORS Murata Electronics CERALOCK resonators have been tested with the ST90158 at 3, 3.68, 4 and 5 MHz. Some resonators have built-in capacitors (see The test circuit is shown in Figure Figure 40. Test circuit Table ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) 6.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the RESET pin. – A ...
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RESET/STOP MANAGER (Cont’d) The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, 55h) written to the appropriate register. The input ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) 7 EXTERNAL MEMORY INTERFACE (EXTMI) 7.1 INTRODUCTION The ST9 External Memory Interface uses two reg- isters (EMR1 and EMR2) to configure external memory accesses. Some interface signals are also affected by WCR - R252 ...
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EXTERNAL MEMORY SIGNALS The access to external memory is made using at least AS, DS, Port 0 and Port 1. RW, DS2, BREQ, BACK and WAIT signals improve functionality but are not always present on ST9 devices. Refer to ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Figure 44. External memory Read/Write with and without a programmable wait n NO WAIT CYCLE T1 SYSTEM CLOCK AS (MC=0) ALE (MC=1) P1 ADDRESS DS (MC=0) P0 ADDRESS MULTIPLEXED RW ...
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EXTERNAL MEMORY SIGNALS (Cont’d) Figure 45. Effects of DS2EN on the behavior of DS and DS2 n SYSTEM CLOCK AS (MC=0) DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED): DS (MC=0) DS (MC=1, READ) DS (MC=1, WRITE) DS2 DS2EN=1 AND LOWER ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) 7.2.4 RW: Read/Write RW (Alternate Function Output, Active low, Tristate) identifies the type of memory cycle: RW=”1” identifies a memory read cycle, RW=”0” identifies a memory write cycle ...
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EXTERNAL MEMORY SIGNALS (Cont’d) Whenever it is sampled low, the System Clock is stretched and the external memory signals (AS, DS, DS2, RW, P0 and P1) are released in high-im- pedance. The external memory interface pins are driven again by ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) 7.3 REGISTER DESCRIPTION EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h DS2EN ASAF x Bit 7 = Reserved. Bit 6 = MC: Mode ...
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REGISTER DESCRIPTION (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0001 1111 (1Fh) 7 MEM - ENCSR DPRREM LAS1 SEL Bit 7 = Reserved. Bit 6 = ENCSR: Enable Code Segment Register. This bit ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) REGISTER DESCRIPTION (Cont’d) Bit 1:0 = UAS[1:0]: Upper memory address strobe stretch . These two bits contain the number of wait cycles (from add to the System Clock to stretch ...
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I/O PORTS 8.1 INTRODUCTION ST9 devices feature flexible individually program- mable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin alloca- tions. These lines, which are logically grouped as 8-bit ports, can be individually programmed to ...
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ST90158 - I/O PORTS PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 ...
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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 49. Control Bits Bit 7 PxC2 PxC27 PxC1 PxC17 PxC0 PxC07 n Table 19. Port Bit Configuration Table ( 1... port number) PXC2n 0 PXC1n 0 PXC0n 0 PXn Configuration ...
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ST90158 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 50. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 51. Input ...
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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output: (Figure 52) – The Output Buffer is turned Open-drain or Push-pull configuration. – The data stored in the Output Master Latch is copied both into the ...
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ST90158 - I/O PORTS 8.5 ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 8.5.1 Pin Declared as I/O A pin ...
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ON-CHIP PERIPHERALS 9.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be connected to exter- nal ...
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ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 9.1.2 Functional Description 9.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to section 9.1.3.1 on page 97. The WDIN Input pin can be used in one ...
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TIMER/WATCHDOG (Cont’d) 9.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input ...
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ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 9.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the ...
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TIMER/WATCHDOG (Cont’d) 9.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS (EIVR.2, Top Level Input ...
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ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 9.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog ...
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TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable . This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and cleared by software. 0: ...
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ST90158 - STANDARD TIMER (STIM) 9.2 STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected ...
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STANDARD TIMER (Cont’d) 9.2.2 Functional Description 9.2.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the ...
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ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 9.2.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled ...
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STANDARD TIMER (Cont’d) 9.2.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8 Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE ...
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ST90158 - MULTIFUNCTION TIMER (MFT) 9.3 MULTIFUNCTION TIMER (MFT) 9.3.1 Introduction The Multifunction Timer (MFT) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic PWM generation and frequency measurement. The MFT comprises a 16-bit Up/Down counter ...
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MULTIFUNCTION TIMER (Cont’d) The configuration of each input is programmed in the Input Control Register. Each of the two output pins can be driven from any of three possible sources: – Compare Register 0 logic – Compare Register 1 logic ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.3.2 Functional Description The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR). 9.3.2.1 Trigger Events A trigger event may be generated ...
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MULTIFUNCTION TIMER (Cont’d) 9.3.2.8 Free Running Mode The timer counts continuously ( down mode) and the counter value simply overflows or underflows through FFFFh or zero; there is no End Of Count condition as such, and no reloading ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Every software or external trigger event on REG0R performs a reload from REG0R resetting the Biload cycle. In One Shot mode (reload initiat software external trigger), reloading ...
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MULTIFUNCTION TIMER (Cont’d) 9.3.3 Input Pin Assignment The two external inputs (TxINA and TxINB) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both rising and falling edges) by ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.3.3.1 TxINA = I/O - TxINB = I/O Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be ...
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MULTIFUNCTION TIMER (Cont’d) 9.3.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.3.3.13 Autodiscrimination Mode The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and ...
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MULTIFUNCTION TIMER (Cont’d) 9.3.4 Output Pin Assignment Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define the driver for ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to ...
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MULTIFUNCTION TIMER (Cont’d) 9.3.5 Interrupt and DMA 9.3.5.1 Timer Interrupt The timer has 5 different Interrupt sources, be- longing to 3 independent groups, which are as- signed to the following Interrupt vectors: Table 23. Timer Interrupt Structure Interrupt Source Vector ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) Figure 63. Pointer Mapping for Register to Register Transfers Register File 8 bit Counter XXXXXX11 8 bit Addr Pointer XXXXXX10 8 bit Counter XXXXXX01 8 bit Addr Pointer XXXXXX00 9.3.5.4 DMA Transaction ...
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MULTIFUNCTION TIMER (Cont’d) 9.3.5.6 DMA End Of Block Interrupt Routine An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for the two channels ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined 7 R15 R14 R13 R12 R11 This register is used to capture values from the Up/Down counter ...
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MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CCP CCMP CEN CCL UDC 0 0 Bit 7 = CEN: Counter enable . This bit is ANDed with the Global ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER MODE REGISTER (TMR) R249 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 OE1 OE0 BM RM1 RM0 ECK REN Bit 7 = OE1: Output 1 enable. 0: Disable ...
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MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 IN3 IN2 IN1 IN0 A0 Bits 7:4 = IN[3:0]: Input pin function. These bits are set and cleared by software. TxINA ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT A CONTROL REGISTER (OACR) R252 - Read/Write Register Page: 10 Reset value: 0000 0000 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P Note: Whenever more than one event occurs si- ...
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MULTIFUNCTION TIMER (Cont’d) OUTPUT B CONTROL REGISTER (OBCR) R253 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P Note: Whenever more than one event occurs si- multaneously, the action taken ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CP0 CP1 CM0 CM1 OUF Bit 7 = CP0: Capture 0 flag. This bit is set by ...
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MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 GT- CM0 CP0D CP0I CP1I IEN D Bit 7 = GTIEN: Global timer interrupt enable . This bit is set and ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined 7 DAP DAP DAP5 DAP4 DAP3 DAP2 7 6 Bits 7:2 = DAP[7:2]: MSB of DMA address regis- ...
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MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) 7 DCT SWE CPE CME DCTS D N Bit 7 = CPE: Capture 0 EOB . This bit is set by hardware ...
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ST90158 - STANDARD TIMER (STIM) 9.4 STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected ...
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STANDARD TIMER (Cont’d) 9.4.2 Functional Description 9.4.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the ...
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ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 9.4.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled ...
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STANDARD TIMER (Cont’d) 9.4.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8 Bits 7:0 = ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) 9.5 SERIAL PERIPHERAL INTERFACE (SPI) 9.5.1 Introduction The Serial Peripheral Interface (SPI general purpose on-chip shift register peripheral. It allows communication with external peripherals via an SPI protocol bus. In addition, special ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.3 Functional Description The SPI, when enabled, receives input data from the internal data bus to the SPI Data Register (SPIDR). A Serial Clock (SCK) is generated by controlling through software two bits in the SPI ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 67. SPI I/O Pins n SCK SDO SDI PORT BIT LATCH PORT BIT LATCH PORT BIT LATCH INT2 136/199 9 9.5.4 Interrupt Structure The SPI peripheral is associated with ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.5 Working With Other Protocols The SPI peripheral offers the following facilities for 2 operation with S-bus/I C-bus and IM-bus proto- cols: Interrupt request on start/stop detection Hardware clock synchronisation Arbitration lost flag with an automatic ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 2 Table 26. Typical I C-bus Sequences Phase SPICR.CPOL, CPHA = 0, 0 SPICR.SPEN = 0 SPICR.BMS = 1 INITIALIZE SCK pin set as AF output SDI pin set as ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) The data on the SDA line is sampled on the low to high transition of the SCL line. 2 SPI working with an I C-bus 2 To use the SPI with the I C-bus protocol, the ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.7 S-Bus Interface The S-bus is a three-wire bidirectional data-bus, possessing functional features similar to the I 2 bus. As opposed to the I C-bus, the Start/Stop conditions are determined ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.8 IM-bus Interface The IM-bus features a bidirectional data line and a clock line; in addition, it requires an IDENT line to distinguish an address byte from a data byte 2 ure 74). Unlike the I ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 9.5.9 Register Description It is possible to have independent SPIs in the same device (refer to the device block dia- gram). In this case they are named ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Bit 2 = CPHA: Transmission Clock Phase. CPHA controls the relationship between the data on the SDI and SDO pins, and the clock signal on the SCK pin. The CPHA bit selects the clock edge used ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 9.6 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) 9.6.1 Introduction The Multiprotocol Serial Communications Inter- face (SCI-M) offers full-duplex serial data ex- change with a wide range of external equipment. The SCI-M offers four operating ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.3 Functional Description The SCI-M has four operating modes: – Asynchronous mode – Asynchronous mode with synchronous clock – Serial expansion mode – Synchronous mode Figure 77. SCI ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4 SCI-M Operating Modes 9.6.4.1 Asynchronous Mode In this mode, data and clock can be asynchronous (the transmitter and receiver can use their own clocks to sample received ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.4.3 Serial Expansion Mode This mode is used to communicate with an exter- nal synchronous peripheral. The transmitter only provides the clock waveform during the period that data ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 79. SCI -M Operating Modes DATA I/O START BIT 16 16 CLOCK Asynchronous Mode I/O DATA START BIT (Dummy) CLOCK Serial Expansion Mode Note: In all operating ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.5 Serial Frame Format Characters sent or received by the SCI can have some or all of the features in the following format, depending on the operating mode: ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.5.1 Data transfer Data to be transmitted by the SCI is first loaded by the program into the Transmitter Buffer Register. The SCI will transfer the data into ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 81. Auto Echo Configuration TRANSMITTER RECEIVER All modes except Synchronous Figure 82. Loop Back Configuration LOGICAL 1 TRANSMITTER RECEIVER All modes except Synchronous Figure 83. Auto Echo ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.6 Clocks And Serial Transmission Rates The communication bit rate of the SCI transmitter and receiver sections can be provided from the in- ternal Baud Rate Generator or ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 28. SCI-M Baud Rate Generator Divider Values Example 1 Baud Clock Desired Freq Rate Factor 50. 75. 110. 300. ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.8 Input Signals SIN: Serial Data Input. This pin is the serial data input to the SCI receiver shift register. TXCLK: External Transmitter Clock Input. This pin is ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.10 Interrupts and DMA 9.6.10.1 Interrupts The SCI can generate interrupts as a result of sev- eral conditions. Receiver interrupts include data pending, receive errors (overrun, framing and ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 31. SCI-M Interrupt Vectors Interrupt Source Transmitter Buffer or Shift Register Empty Transmit DMA end of Block Received Data Pending Receive DMA end of Block Break Detector ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.10.2 DMA Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.6.11 Register Description The SCI-M registers are located in the following pages in the ST9: SCI-M number 0: page 24 (18h) SCI-M number 1: page 25 (19h) (when ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER DMA COUNTER POINTER (RDCPR) R240 - Read/Write Reset value: undefined 7 RC7 RC6 RC5 RC4 RC3 Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer. These bits contain ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (S_IVR) R244 - Read/Write Reset value: undefined Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad- dress. User programmable ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (IMR) R246 - Read/Write Reset value: 0xx00000 7 BSN RXEOB TXEOB RXE RXA Bit 7 = BSN: Buffer or shift register empty inter- rupt . ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (S_ISR) R247 - Read/Write Reset value: undefined RXAP RXBP RXDP TXBEM TXSEM Bit 7 = OE: Overrun Error Pending . This ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER BUFFER REGISTER (RXBR) R248 - Read only Reset value: undefined 7 RD7 RD6 RD5 RD4 RD3 Bit 7:0 = RD[7:0]: Received Data. This register stores the data ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT/DMA PRIORITY REGISTER (IDPR) R249 - Read/Write Reset value: undefined 7 AMEN SB SA RXD TXD PRL2 Bit 7 = AMEN: Address Mode Enable. This bit, together with ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CHARACTER CONFIGURATION (CHCR) R250 - Read/Write Reset value: undefined PEN AB SB1 Bit 7 = AM: Address Mode . This bit, together with the AMEN ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) CLOCK CONFIGURATION REGISTER (CCR) R251 - Read/Write Reset value: 0000 0000 (00h) 7 XTCLK OCLK XRX XBRG CD AEN Bit 7 = XTCLK This bit, together with the ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) BAUD RATE GENERATOR HIGH REGISTER (BRGHR) R252 - Read/Write Reset value: undefined 15 BG15 BG14 BG13 BG12 BG11 BAUD RATE GENERATOR LOW REGISTER (BRGLR) R253 - Read/Write Reset ...
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ST90158 - MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d) SYNCHRONOUS OUTPUT CONTROL (SOCR) R255 - Read/Write Reset value: 0000 0001 (01h) 7 OUTP OUTS OCKP OCKS RTSE Bit 7 = OUTPL: SOUT ...
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MIRROR REGISTER (MR) 9.7.1 Introduction The Mirror Register transforms the bit order of a byte from Most Significant Bit first (MSB-first) to Least Significant Bit first (LSB-first) or vice versa. This feature can be used, for example, when pro- ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) 9.8 EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) 9.8.1 Introduction The 8-Channel Analog to Digital Converter (A/D) comprises an input multiplex channel selector feeding a successive approximation converter. Conversion requires 138 INTCLK cycles ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Single and continuous conversion modes are available. Conversion may be triggered by an ex- ternal signal or, internally, by the Multifunction Timer. A Power-Down programmable bit allows ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Analog channels 6 and 7 monitor an acceptable voltage level window for the converted analog in- puts. The external voltages applied to inputs 6 and 7 are ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Figure 89. Application Example: Analog Watchdog used in Motorspeed Control n 9.8.3 Interrupts The A/D provides two interrupt sources: – End of Conversion – Analog Watchdog Request ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) 9.8.4 Register Description DATA REGISTERS (DiR) The conversion results for the 8 available chan- nels are loaded into the 8 Data registers following conversion of the corresponding ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) CHANNEL 6 LOWER THRESHOLD REGISTER (LT6R) R248 - Read/Write Register Page: 63 Reset Value: undefined 7 LT6.7 LT6.6 LT6.5 LT6.4 LT6.3 LT6.2 LT6.1 LT6.0 Bit 7:0 = ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) CONTROL LOGIC REGISTER (CLR) The Control Logic Register (CLR) manages the A/D converter logic. Writing to this register will cause the current conversion to be aborted and ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) INTERRUPT CONTROL REGISTER (AD_ICR) R254 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh) 7 ECV AWD ECI AWDI X Bit 7 = ECV: End of ...
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ST90158 - ELECTRICAL CHARACTERISTICS 10 ELECTRICAL CHARACTERISTICS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...
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DC ELECTRICAL CHARACTERISTICS ( ± 10 -40°C + 85°C, INTCLK = 24 MHz unless otherwise specified Symbol Parameter V Clock Input High Level IHCK V Clock Input Low Level ILCK V Input High Level ...
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ST90158 - ELECTRICAL CHARACTERISTICS AC ELECTRICAL CHARACTERISTICS ( ± 10 -40°C + 85°C, INTCLK = 24 MHz unless otherwise specified Symbol I Run Mode Current, PLL on DDRUN I WFI Mode Current, PLL on ...
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EXTERNAL BUS TIMING TABLE ( ± 10 -40°C + 85°C, Cload = 50pF, INTCLK = 16MHz, unless otherwise specified N° Symbol 1 TsA (AS) Address Set-up Time before AS 2 ThAS (A) Address Hold ...
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ST90158 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING 182/199 9 ...
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EXTERNAL INTERRUPT TIMING TABLE ( ± 10 -40°C +85°C, Cload = 50pF, INTCLK = 12MHz, Push-pull output configuration, un less otherwise specified) N° Symbol Parameter Low Level Minimum Pulse Width in Rising 1 TwLR ...
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ST90158 - ELECTRICAL CHARACTERISTICS SPI TIMING TABLE ( ± 10 -40°C + 85°C, Cload = 50pF, INTCLK = 12MHz, Output Alternate Function set Push-pull) N° Symbol 1 TsDI Input Data Set-up Time 2 ...
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SCI TIMING TABLE ( 10 40°C to +105°C, C – Symbol Parameter F Frequency of RxCKIN RxCKIN Tw RxCKIN shortest pulse RxCKIN F Frequency of TxCKIN TxCKIN Tw TxCKIN shortest pulse TxCKIN DS ...
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ST90158 - ELECTRICAL CHARACTERISTICS WATCHDOG TIMING TABLE ( ± 10 -40°C + 85°C, Cload = 50pF, INTCLK = 12MHz, Push-pull output configuration unless otherwise specified ) N° Symbol 1 TwWDOL WDOUT Low Pulse Width ...
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STANDARD TIMER TIMING TABLE ( 10 40°C to +105°C, C – unless otherwise specified) N° Symbol Parameter 1 TwSTOL STOUT Low Pulse Width 2 TwSTOH STOUT High Pulse Width 3 TwSTIL STIN High Pulse ...
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ST90158 - ELECTRICAL CHARACTERISTICS MULTIFUNCTION TIMER EXTERNAL TIMING TABLE ( 10 40°C to +105°C, C – N° Symbol 1 Tw External clock/trigger pulse width CTW 2 Tw External clock/trigger pulse distance CTD 3 Tw ...
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A/D EXTERNAL TRIGGER TIMING TABLE N° Symbol Parameter 1 Tw External trigger pulse width LOW 2 Tw External trigger pulse distance HIGH External trigger active edges 3 Tw EXT distance (1) EXTRG falling edge and first 4 Td STR conversion ...
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ST90158 - ELECTRICAL CHARACTERISTICS A/D INTERNAL TRIGGER TIMING TABLE N° Symbol Parameter Internal trigger 1 Tw HIGH pulse width Internal trigger 2 Tw LOW pulse distance Internal trigger 3 Tw active edges EXT distance (1) Internal delay between INTRG 4 ...
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A/D CHANNEL ENABLE TIMING TABLE ( ± 10 40°C to +105°C, C – N° Symbol 1 Tw CEn Pulse width EXT Note: The value in the left hand column shows the formula used to ...
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ST90158 - ELECTRICAL CHARACTERISTICS A/D ANALOG SPECIFICATIONS ( ± 10 40°C to +105°C, f – Parameter Conversion time Sample time Power-up time Resolution Monotonicity No missing codes Zero input reading Full scale reading Offset ...
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MULTIFUNCTION TIMER EXTERNAL TIMING TABLE ( 10 40°C to +105°C, C – N° Symbol 1 Tw External clock/trigger pulse width CTW 2 Tw External clock/trigger pulse distance CTD 3 Tw Distance between two active ...
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ST90158 - ELECTRICAL CHARACTERISTICS SCI TIMING TABLE ( 10 40°C to +105°C, C – Symbol Parameter F Frequency of RxCKIN RxCKIN Tw RxCKIN shortest pulse RxCKIN F Frequency of TxCKIN TxCKIN Tw TxCKIN ...
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GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA Figure 90. 80-Pin Thin Plastic Quad Flat Package Figure 91. 80-Pin Plastic Quad Flat Package ST90158 - GENERAL INFORMATION 0.10mm Dim .004 Min seating plane A A1 0.05 A2 1.35 1.40 1.45 0.053 ...
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ST90158 - GENERAL INFORMATION 80-Pin Ceramic Quad Flat Package 196/199 1 Dim 19.57 20.00 20.43 0.770 0.787 0.804 13.61 14.00 14.39 0.536 0.551 0.567 19.75 20.00 20.25 ...
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ORDERING INFORMATION ( 10%) DD Program Part Number Memory (Bytes) ST90135M5Q6 24K ROM ST90135M5T6 ST90135M6Q6 32K ROM ST90135M6T6 ST90158M7Q6 48K ROM ST90158M7T6 ST90158M9Q6 64K ROM ST90158M9T6 ST90E158M9G0 64K EPROM ST90T158M9Q6 64K OTP ST90T158M9T6 ST90R158Q6 ROMless ST90R158T6 (V ...
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... ST90158 - GENERAL INFORMATION ST90135/158 OPTION LIST (ROM DEVICE) Please copy this page (enlarge if possible) and complete ALL sections. Send the form, with the ROM code image required, to your local STMicroelectronics sales office. Customer Address Phone No Fax Contact Please confirm the characteristics of the ST9 device: ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...