5M2210ZF256C5N Altera, 5M2210ZF256C5N Datasheet - Page 63

• Manufacturer Part Number: 5M2210ZF256C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M2210ZF256C5N

• Cpld Type: FLASH
• No. Of Macrocells: 1700
• No. Of I/o's: 271
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 201.1MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 2210
• Number Of Macrocells: 1700
• Number Of Gates: -
• Number Of I /o: 203
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
Table 3–28. Global Clock External I/O Timing Parameters for the 5M570Z Device
Table 3–29. Global Clock External I/O Timing Parameters for the 5M1270Z Device
May 2011 Altera Corporation
t
t
t
t
t
t
t
t
f
Note to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
t
t
t
t
t
t
t
t
f
Notes to
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
(2) Not applicable to the F324 package of the 5M1270Z device.
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
PD1
PD2
SU
H
CO
CH
CL
CNT
CNT
Symbol
Symbol
clock input pin maximum frequency.
clock input pin maximum frequency.
Table
Table
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
Worst case pin-to-pin delay through one LUT
Best case pin-to-pin delay through one LUT
Global clock setup time
Global clock hold time
Global clock to output delay
Global clock high time
Global clock low time
Minimum global clock period for 16-bit
counter
Maximum global clock frequency for 16-bit
counter
3–28:
3–29:
Table 3–28
Table 3–29
Parameter
Parameter
lists the external I/O timing parameters for the 5M570Z device.
lists the external I/O timing parameters for the 5M1270Z device.
Condition
Condition
10 pF
10 pF
10 pF
10 pF
10 pF
10 pF
—
—
—
—
—
—
—
—
—
—
—
—
Min
253
253
2.2
2.0
5.4
—
—
—
Min
216
0
216
2.0
1.5
4.0
—
—
—
0
C4
C4
(Note 1)
184.1
(Note
Max
247.5
9.5
5.7
6.7
—
—
—
—
—
Max
8.1
4.8
5.9
—
—
—
—
—
1),
(2)
Min
339
339
4.4
2.0
8.4
—
—
—
Min
0
266
266
1.9
2.0
5.0
—
—
—
0
C5, I5
C5, I5
MAX V Device Handbook
118.3
17.7
Max
8.5
8.7
201.1
—
—
—
—
—
Max
10.0
5.9
7.3
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
ps
ps
ns
MHz
Unit
3–21
ns
ns
ns
ns
ns
ps
ps
ns