5M80ZT100C5N Altera, 5M80ZT100C5N Datasheet - Page 36

• Manufacturer Part Number: 5M80ZT100C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M80ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 64
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 80
• Number Of Macrocells: 64
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2–24
MAX V Device Handbook
UFM Block to Logic Array Interface
The UFM block is a small partition of the flash memory that contains the CFM block,
as shown in
5M160Z, and 5M240Z devices is located on the left side of the device adjacent to the
left most LAB column. The UFM blocks for the 5M570Z, 5M1270Z, and 5M2210Z
devices are located at the bottom left of the device. The UFM input and output signals
interface to all types of interconnects (R4 interconnect, C4 interconnect, and
DirectLink interconnect to/from adjacent LAB rows). The UFM signals can also be
driven from global clocks, GCLK[3..0]. The interface regions for the 5M40Z, 5M80Z,
5M160Z, and 5M240Z devices are shown in
5M570Z, 5M1270Z, and 5M2210Z devices are shown in
Figure 2–16. 5M40Z, 5M80Z, 5M160Z, and 5M240Z UFM Block LAB Row Interface
Notes to
(1) The UFM block inputs and outputs can drive to and from all types of interconnects, not only DirectLink interconnects
(2) Not applicable to the T144 package of the 5M240Z device.
from adjacent row LABs.
Figure
Figure 2–1
2–16:
and
Figure
CFM Block
2–2. The UFM block for the 5M40Z, 5M80Z,
UFM Block
RTP_BUSY
PROGRAM
OSC_ENA
DRSHFT
ARSHFT
DRDout
ERASE
DRCLK
ARCLK
DRDin
BUSY
ARin
OSC
Figure
2–16. The interface regions for
Figure
LAB
LAB
LAB
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
2–17.
User Flash Memory Block
(Note
1),
(2)