CAT1023WI-28-GT3 CATALYST SEMICONDUCTOR, CAT1023WI-28-GT3 Datasheet - Page 6
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CAT1023WI-28-GT3
Manufacturer Part Number
CAT1023WI-28-GT3
Description
CPU SUP WITH 2K EEPROM
Manufacturer
CATALYST SEMICONDUCTOR
Datasheet
1.CAT1022WI-25-T3.pdf
(21 pages)
Specifications of CAT1023WI-28-GT3
No. Of Supervisors / Monitors
1
Supply Voltage Range
2.7V To 5.5V
Reset Type
Manual, Active-High / Active-Low
Supply Current
3mA
Digital Ic Case Style
SOIC
No. Of Pins
8
Threshold Voltage
3V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CAT1023WI-28-GT3
Manufacturer:
ON
Quantity:
50 000
Part Number:
CAT1023WI-28-GT3
Manufacturer:
CATALYS
Quantity:
20 000
CAT1021, CAT1022, CAT1023
RESET CIRCUIT AC CHARACTERISTICS
POWER-UP TIMING
AC TEST CONDITIONS
RELIABILITY CHARACTERISTICS
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage V
(3) Power-Down, Input Reference Voltage V
(4) V
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) t
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to V
Doc. No. MD-3009 Rev. P
Parameter
Input Pulse Voltages
Input Rise and Fall times
Input Reference Voltages
Output Reference Voltages
Output Load
Symbol
MR Glitch
I
N
V
Symbol
LTH
T
Symbol
t
PUR
t
END
ZAP
GLITCH
DR
CC
PURST
t
t
t
MRW
t
MRD
RDP
t
(5)(7)
t
WD
PUW
PUR
(5)
Glitch Reference Voltage = V
and t
(5)
(5)
PUW
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
are the delays required from the time V
Parameter
Power-Up Reset Timeout
V
V
Manual Reset Glitch Immunity
MR Pulse Width
MR Input to RESET Output Delay
Watchdog Timeout
TH
CC
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
to RESET output Delay
Glitch Reject Pulse Width
(5), (6)
THmin
CC
; Based on characterization data
= V
CC
Current Source: I
MIL-STD-883, Test Method 1033
= V
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
TH
Reference Test Method
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
JEDEC Standard 17
CC
0.2 x V
0.3 x V
is stable until the specified memory operation can be initiated.
Test Conditions
0.5
CC
CC
10 ns
OL
Test Conditions
Test Conditions
to 0.8 x V
6
x
= 3 mA; C
, 0.7 x V
V
Note 4, 5
CC
Note 1
Note 2
Note 3
Note 1
Note 1
Note 1
CC
CC
L
= 100 pF
1,000,000
Min
130
Min
1.0
2000
5
Min
100
100
CC
+ 1 V.
Characteristics subject to change without notice
Typ
200
Typ
1.6
Max
© 2009 SCILLC. All rights reserved.
Max
270
100
Max
270
270
2.1
30
5
1
Cycles/Byte
Years
Units
Volts
mA
Units
Units
sec
ms
ms
µs
ns
µs
µs
ms
ns