24LC128T-I/MF Microchip Technology, 24LC128T-I/MF Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
24LC128T-I/MF
Manufacturer Part Number
24LC128T-I/MF
Description
IC,SERIAL EEPROM,16KX8,CMOS,LLCC,8PIN,PLASTIC
Manufacturer
Microchip Technology
Datasheet
1.24LC128-ISN.pdf
(38 pages)
Specifications of 24LC128T-I/MF
Rohs Compliant
YES
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
128K (16K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
24LC128T-I/MF
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
24LC128T-I/MF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
The A0, A1 and A2 inputs are used by the 24XX128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either V
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2010 Microchip Technology Inc.
A0
A1
(NC)
A2
V
SDA
SCL
WP
V
Note 1:
SS
CC
Name
PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
Serial Data (SDA)
The exposed pad on the DFN/TDFN package can be connected to V
CC
PDIP
—
1
2
3
4
5
6
7
8
(typical 10 k for 100 kHz, 2 k for
PIN FUNCTION TABLE
CC
SOIC
—
or V
1
2
3
4
5
6
7
8
SS
.
TSSOP
—
1
2
3
4
5
6
7
8
MSOP
1, 2
—
—
24AA128/24LC128/24FC128
3
4
5
6
7
8
DFN
—
1
2
3
4
5
6
7
8
(1)
2.3
This input is used to synchronize the data transfer to
and from the device.
2.4
This pin must be connected to either V
to V
write operations are inhibited but read operations are
not affected.
3.0
The 24XX128 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions while the
24XX128 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
TDFN
—
SS
1
2
3
4
5
6
7
8
, write operations are enabled. If tied to V
(1)
Serial Clock (SCL)
Write-Protect (WP)
FUNCTIONAL DESCRIPTION
CS
—
3
2
5
8
6
7
4
1
SS
or left floating.
User Configurable Chip Select
User Configurable Chip Select
Not Connected
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7V to 5.5V (24AA128)
+2.5V to 5.5V (24LC128)
+1.7V to 5.5V (24FC128)
Function
DS21191S-page 5
SS
or V
CC
. If tied
CC
,