5M1270ZF256I5N Altera, 5M1270ZF256I5N Datasheet - Page 145
5M1270ZF256I5N
Manufacturer Part Number
5M1270ZF256I5N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M1270ZF256I5N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
6.2ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
1270
Number Of Macrocells
980
Number Of Gates
-
Number Of I /o
211
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M1270ZF256I5N
Manufacturer:
ALTERA12
Quantity:
813
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Chapter 7: User Flash Memory in MAX V Devices
Simulation Parameters
Simulation Parameters
Document Revision History
Table 7–17. Document Revision History
January 2011 Altera Corporation
January 2011
December 2010
Date
Padding Data into Memory Map
The ALTUFM_I2C megafunction uses the upper 8 bits of the UFM 16-bit word;
therefore, the 8 least significant bits should be padded with 1s, as shown in
Figure
Figure 7–41. Padding Data into Memory Map
In the ALTUFM megafunction, you have an option to simulate the OSC output port at
the maximum or the minimum frequency during the design simulation. The
frequency chosen is only used as the timing parameter for the Quartus II simulator
and does not affect the real MAX V device OSC output frequency.
Table 7–17
Version
1.1
1.0
7–41.
lists the revision history for this chapter.
1
Updated
Initial release.
0
8-bit valid data to be placed
in the upper byte
1
“Oscillator”
0
1
0
section.
1
0
1
Changes
Pad the lower byte with eight '1's
1
1
1
1
1
MAX V Device Handbook
1
1
7–43
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