5M2210ZF256C4N Altera, 5M2210ZF256C4N Datasheet - Page 38
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5M2210ZF256C4N
Manufacturer Part Number
5M2210ZF256C4N
Description
ALTERA
Manufacturer
Altera
Series
MAX® Vr
Specifications of 5M2210ZF256C4N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.0ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
2210
Number Of Macrocells
1700
Number Of Gates
-
Number Of I /o
203
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M2210ZF256C4N
Manufacturer:
ALTERA
Quantity:
73
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2–26
I/O Structure
MAX V Device Handbook
IOEs support many features, including:
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MAX V device IOEs contain a bidirectional I/O buffer.
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s
bidirectional I/O buffers. The Quartus II software automatically attempts to place
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible
clock-to-output and registered output enable timing. When the fast input registers
option is enabled, the Quartus II software automatically routes the register to
guarantee zero hold time. You can set timing assignments in the Quartus II software
to achieve desired I/O timing.
LVTTL, LVCMOS, LVDS, and RSDS I/O standards
3.3-V, 32-bit, 33-MHz PCI compliance
JTAG boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
Figure 2–19
December 2010 Altera Corporation
Chapter 2: MAX V Architecture
shows the MAX V
I/O Structure
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