A3946KLPTR-T Allegro Microsystems Inc, A3946KLPTR-T Datasheet - Page 7

• Manufacturer Part Number: A3946KLPTR-T
• Description: IC,Motor Controller,BCDMOS,TSSOP,16PIN
• Manufacturer: Allegro Microsystems Inc

Specifications of A3946KLPTR-T

• Applications: DC Motor Controller, Brushless (BLDC), 3 Phase
• Number Of Outputs: 1
• Voltage - Supply: 7 V ~ 60 V
• Operating Temperature: -40°C ~ 135°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Load: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 620-1295-2; A3946KLPTR-T

A3946
Dead Time. The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When in struct ed to
turn off, the gate outputs change after an short internal propa-
gation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, t
to 6000 ns using the following formula:
where t
range 5 kΩ < R
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 μs.
Control Logic. Two different methods of control are
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by short-
ing IN1 with IN2. If a very slow turn-on is required (greater
than 6 μs), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
Fault Response Table
No Fault
BOOT Capacitor Undervoltage
VREG Undervoltage
VREF Undervoltage
Thermal Shutdown
Sleep
1
2
3
though ~FAULT = 0.
4
5
come high impedance (High Z). Refer to the section Sleep Mode/Power Up.
(IL) indicates that the state is determined by the input logic.
This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
These faults are latched. Clear by pulsing RESET = 0. Note that outputs become active as soon as VREG comes out of undervoltage, even
Unspecifi ed VREF undervoltage threshold < 4 V.
During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to be-
5
DEAD
Fault Mode
is in ns, and R
DEAD
DEAD
, can be adjusted within the range 350 ns
3
< 100 kΩ.
t
4
3
DEAD
= 50 + (R
DEAD
is in Ω, and should be in the
2
DEAD
RESET
⁄ 16.7 )
1
1
1
1
1
0
~FAULT
1
0
0
0
0
1
Half-Bridge Power MOSFET Controller
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Top-Off Charge Pump. An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount of
bias current is drawn from the BOOT pin to operate the fl oat-
ing high-side circuit. The top-off charge pump simply pro-
vides enough drive to ensure that the gate voltage does not
droop due to this bias supply current. The charge required for
initial turn-on of the high-side gate must be supplied by boot-
strap capacitor charge cycles. This is described in the section
Application Information.
VREF. VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 μF
capacitor is needed for decoupling.
VREG
OFF
OFF
ON
ON
ON
ON
VREF
OFF
ON
ON
ON
ON
ON
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
High Z
GH
(IL)
(IL)
0
0
0
1
High Z
GL
(IL)
(IL)
(IL)
0
0
1
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