ACS710KLATR-6BB-T Allegro Microsystems Inc, ACS710KLATR-6BB-T Datasheet - Page 12

• Manufacturer Part Number: ACS710KLATR-6BB-T
• Description: CURRENT SENSOR WITH INTEGRATED OVERCURRENT DETECTION
• Manufacturer: Allegro Microsystems Inc
• Series: -r

Specifications of ACS710KLATR-6BB-T

• Current - Sensing: ±6A
• Accuracy: ±4.05%
• Sensitivity: 100mV/A
• Current - Supply: 11mA
• Sensor Type: Hall Effect
• Voltage - Supply: 3 V ~ 5.5 V
• Output: 2.5V
• Frequency: 120kHz
• Response Time: 4µs
• Polarization: Bidirectional
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-SOIC (0.295", 7.50mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ACS710
Overcurrent Fault Operation
The primary concern with high-speed fault detection is that noise
may cause false tripping. Various applications have or need to
be able to ignore certain faults that are due to switching noise or
other parasitic phenomena, which are application dependant. The
problem with simply trying to filter out this noise in the main
signal path is that in high-speed applications, with asymmetric
noise, the act of filtering introduces an error into the measure-
ment. To get around this issue, and allow the user to prevent the
fault signal from being latched by noise, a circuit was designed to
slew the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin voltage based on the value of the capacitor
from that pin to ground. Once the voltage on the pin falls below
2 V, as established by an internal reference, the fault output is
latched and pulled to ground quickly with an internal N-channel
MOSFET.
Fault Walk-through
The following walk-through references various sections and
attributes in the figure below. This figure shows different
fault set/reset scenarios and how they relate to the voltages on
the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin, FAULT_EN pin, and the internal Overcurrent
(OC) Fault node, which is invisible to the customer.
1. Because the device is enabled (FAULT_EN is high for a
(Active High)
minimum period of time, the Fault Enable Delay, t
typical) and there is an OC fault condition, the device ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
pin starts discharging.
FAULT_EN
Condition
OC Fault
(Output)
FAULT
(Input)
V
2 V
0 V
CC
1
4
Current Sensor with Integrated Overcurrent Detection
2
3
Functional Description
FED
6
120 kHz Bandwidth, High Voltage Isolation
, 15 μs
Time
t
FED
2. When the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin voltage reaches approximately 2 V, the
3. When the FAULT_EN pin is brought low, the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
4. The slope, and thus the delay to latch the fault is controlled by
1
fault is latched, and an internal NMOS device pulls the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
pin voltage to approximately 0 V. The rate at which the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯
pin slews downward (see [4] in the figure) is dependent on the
external capacitor, C
pin starts resetting if no OC fault condition exists, and if
FAULT_EN is low for a time period greater than t
internal NMOS pull-down turns off and an internal PMOS pull-
up turns on (see [7] if the OC fault condition still exists).
the capacitor, C
ing this portion of the fault (when the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin is between
V
discharges C
where V
seconds and C
equal to or greater than 330 kΩ. For lower-value resistors,
the current flowing through the R
event, I
the capacitor would be 3 mA – I
valid.
CC
4
and 2 V), there is a 3 mA constant current sink, which
5
PU
CC
6
, will be larger. Therefore, the current discharging
is the device power supply voltage in volts, t is in
OC
OC
t =
. The length of the fault delay, t, is equal to:
OC
1
is in Farads. This formula is valid for R
, placed on the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin to ground. Dur-
C
OC
OC
, on the ¯ F ¯ ¯ A ¯ ¯ U ¯ ¯ L ¯ ¯ T ¯ pin.
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
4
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
( V
3 mA
CC
– 2 V )
PU
2
PU
and equation 1 may not be
resistor during a fault
7
6
8
OCH
4
. The
2
PU
(1)
12