AD1836AASZRL Analog Devices Inc, AD1836AASZRL Datasheet
AD1836AASZRL
Specifications of AD1836AASZRL
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AD1836AASZRL Summary of contents
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FEATURES 5 V multichannel audio system Accepts 16-/18-/20-/24-bit data Supports 24-bit and 96 kHz sample rate Multibit Σ-∆ modulators with data directed scrambling Differential output for optimum performance ADCs: –92 dB THD + N, 105 dB SNR and dynamic range ...
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AD1836A TABLE OF CONTENTS AD1836A—Specifications ............................................................... 3 Absolute Maximum Ratings............................................................ 8 Pin Configuration And Pin Functional Descriptions.................. 9 Functional Overview...................................................................... 11 ADCs............................................................................................ 11 DACs ............................................................................................ 11 Clock Signals ............................................................................... 11 Reset and Power-Down ............................................................. 12 REVISION HISTORY Revision 0: Initial ...
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AD1836A—SPECIFICATIONS Table 1. Test conditions, unless otherwise noted. Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Parameter Supply Voltages (AVDD, DVDD) Ambient Temperature Master Clock Input Signal Input Sample Rate Measurement ...
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AD1836A Table 2. Analog Performance Parameter ANALOG-TO-DIGITAL CONVERTERS DIGITAL-TO-ANALOG CONVERTERS 1 Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active. 2 Measured with Audio Precision System Two Cascade in ...
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Table 3. Digital I/O Parameter Input Voltage Input Voltage Input Leakage ( 2 Input Leakage ( 0 High Level Output ...
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AD1836A Table 7. Timing Specifications Parameter MASTER CLOCK AND RESET SPI PORT DAC SERIAL PORT (Normal Modes) DAC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) ADC SERIAL PORT (Normal Modes) ADC SERIAL PORT (Packed 128 Mode, Packed 256 Mode) ...
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Table 7. Timing Specifications (Continued) Parameter AUXILIARY INTERFACE (Master Mode) AUXILIARY INTERFACE (Slave Mode) Comments t AUXBCLK Delay From MCLK Transition, 256 × f XBD From MCLK Rising, 512 × AUXLRCLK Skew From AUXBCLK Falling XLS t AUXBCLK ...
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AD1836A ABSOLUTE MAXIMUM RATINGS Table 8. AD1836A Absolute Maximum Ratings Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Stresses above those listed under Absolute Maximum ...
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PIN CONFIGURATION AND PIN FUNCTIONAL DESCRIPTIONS OUTLP3 OUTLN3 OUTLP2 OUTLN2 OUTLP1 OUTLN1 Table 10. Pin Function Descriptions—52-Lead MQFP Pin No. In/Out Mnemonic 1 I DVDD 2 I CDATA 3 I PD/RST 4 O OUTLP3 5 O OUTLN3 6 O OUTLP2 ...
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AD1836A Pin No. In/Out Mnemonic 27 I ADC2INRP/CAPR2 28 I AGND 29 I AGND 30 O OUTRN1 31 O OUTRP1 32 O OUTRN2 33 O OUTRP2 34 O OUTRN3 35 O OUTRP3 36 I/O DLRCLK 37 I/O DBCLK 38 I ...
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FUNCTIONAL OVERVIEW ADCs There are four ADC channels in the AD1836A configured as two independent stereo pairs. One stereo pair is the primary ADC and has fully differential inputs. The second pair can be programmed to operate in one of ...
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AD1836A through an FPGA or other large digital chip before being applied to the AD1836A. In most cases, this will induce clock jitter due to the fact that the clock signal is sharing common power and ground connections with other ...
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POWER SUPPLY AND VOLTAGE REFERENCE The AD1836A is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the ...
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AD1836A LRCLK LEFT CHANNEL BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK MSB SDATA LRCLK BCLK SDATA MSB NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL 2. LRCLK NORMALLY OPERATES BCLK FREQUENCY ...
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LRCLK 128 BCLKs BCLK 32 BCLKs SLOT 1 SLOT 2 DATA LEFT 0 LEFT 1 MSB MSB–1 MSB–2 Figure 5. ADC Packed Mode 128 LRCLK 256 BCLKs BCLK 32 BCLKs SLOT 1 SLOT 2 DATA SLOT 3 SLOT 4 LEFT ...
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AD1836A FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) INTERNAL ASDATA1 ADC L0 32 MSB TDM DSDATA1 1ST CH TDM (IN) INTERNAL DSDATA1 DAC L0 32 AUX 2 LRCLK I S (FROM AUX ADC NO. 1) AUX 2 ...
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LRCLK BCLK ADC NO. 1 SLAVE DATA MCLK LRCLK DLRCLK/AUXLRCLK BCLK DSDATA2/AAUXDATA1 ADC NO. 2 SLAVE DATA DSDATA3/AAUXDATA2 MCLK MCLK Figure 10. AUX Mode Connection to SHARC (Master Mode) 30MHz 12.288MHz LRCLK BCLK ADC NO. 1 MASTER DATA ...
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AD1836A Table 11. Pin Function Changes in AUX Mode 2 2 Pin Name (I S/AUX Mode Mode 2 ASDATA1( Data Out, Internal ADC1 ASDATA2(O)/DAUXDATA( Data Out, Internal ADC2 2 DSDATA1( Data ...
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SPI CONTROL REGISTERS Note that all control registers default to zero at power-up. Table 12. Serial SPI Word Format Register Address 15:12 4 Bits Table 13. Register Addresses and Functions Register Address Bit 15 Bit 14 Bit 13 Bit 12 ...
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AD1836A Table 15. DAC Control Register 2 Address RD/WR Reserved 15, 14 0001 0 00000 Table 16. DAC Volume Registers Address RD/WR 15, 14, 13 0010: DAC1L 0 0011: DAC1R ...
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Table 19. ADC Control Register 3 When changing clock mode, other SPI bits that are written during the same SPI transaction may be lost. Therefore recommended that these be set separately. Address RD/WR Reserved Clock Mode 15, 14, ...
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AD1836A INPUT NO. 1 INPUT NO. 2 NOTE ADC2 SINGLE-ENDED MUX PGA INPUT MODE––LEFT CHANNEL ONLY SHOWN. CONTROL REGISTER 3 CONTENTS: 6 LSBs: SELECT INPUT NO 1010 LEFT + VE LEFT – VE AD1836A CAP1L C1 1nF – ...
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OUTLINE DIMENSIONS SEATING PLANE VIEW A ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD ...
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AD1836A NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03800–0–8/03(0) Rev Page ...