AD5246BKSZ50-RL7 Analog Devices Inc, AD5246BKSZ50-RL7 Datasheet - Page 5

IC,Digital Potentiometer,TSSOP,6PIN,PLASTIC

AD5246BKSZ50-RL7

Manufacturer Part Number
AD5246BKSZ50-RL7
Description
IC,Digital Potentiometer,TSSOP,6PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5246BKSZ50-RL7

Taps
128
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
45 ppm/°C Typical
Memory Type
Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SC-70-6, SC-88, SOT-363
Resistance In Ohms
50K
Number Of Elements
1
# Of Taps
128
Resistance (max)
50KOhm
Power Supply Requirement
Single
Interface Type
Serial (2-Wire/I2C)
Single Supply Voltage (typ)
3/5V
Dual Supply Voltage (typ)
Not RequiredV
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AD5246BKSZ50-RL7
AD5246BKSZ50-RL7TR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5246BKSZ50-RL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
TIMING CHARACTERISTICS
V
Table 3.
Parameter
I
1
2
3
4
2
Typical specifications represent average readings at 25°C and V
Guaranteed by design; not subject to production test.
See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values.
C INTERFACE TIMING CHARACTERISTICS
Specifications apply to all parts.
DD
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
= 5 V ± 10% or 3 V ± 10%; V
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Bus Free Time Between STOP and START
Low Period of SCL Clock
High Period of SCL Clock
Hold Time (Repeated START)
Setup Time for Repeated START Condition
Setup Time for STOP Condition
Data Setup Time
Data Hold Time
A
= V
DD
2, 3, 4
; –40°C < T
A
DD
f
t
t
Symbol
t
t
t
t
t
t
t
t
< +125°C, unless otherwise noted.
SCL
1
2
3
4
5
6
7
8
9
10
= 5 V.
Rev. B | Page 5 of 16
Conditions
After this period, the first clock pulse is
generated
Min
1.3
0.6
1.3
0.6
0.6
100
0.6
Typ
1
Max
400
50
0.9
300
300
AD5246
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs

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