AD5274BCPZ-100-RL7 Analog Devices Inc, AD5274BCPZ-100-RL7 Datasheet - Page 20

• Manufacturer Part Number: AD5274BCPZ-100-RL7
• Description: 256 Tap 5v 50tp, 1% R-tol MSOP 12C I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD5274BCPZ-100-RL7

• Resistance (ohms): 100K
• Taps: 256
• Number Of Circuits: 1
• Temperature Coefficient: 5 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.5 V ~ 2.75 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AD5274BCPZ-100-RL7; AD5274BCPZ-100-RL7TR

AD5272/AD5274
READ OPERATION
When reading data back from the AD5272/AD5274, the user
must first issue a readback command to the device, this begins
with a start command followed by an address byte (R/ W = 0),
after which the AD5272/AD5274 acknowledges that it is
prepared to receive data by pulling SDA low.
Two bytes of data are then written to the AD5272/AD5274, the
most significant byte followed by the least significant byte; both
of these data bytes are acknowledged by the AD5272/AD5274.
SDA
SDA
SCL
SCL
START BY
START BY
MASTER
MASTER
0
1
0
1
1
1
SERIAL BUS ADDRESS BYTE
SERIAL BUS ADDRESS BYTE
0
0
SDA (CONTINUED)
SDA (CONTINUED)
SCL (CONTINUED)
SCL (CONTINUED)
FRAME 1
FRAME 1
1
1
1
1
A1
A1
A0
A0
Figure 45. Read Command
AD5272/AD5274
R/W
R/W
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9
ACK. BY
ACK. BY
AD5272/AD5274
D7
1
D7
9
1
9
D6
1
0
D6
0
1
A stop condition follows. These bytes contain the read instruc-
tion, which enables readback of the RDAC register, 50-TP
memory, or the control register. The user can then read back
the data beginning with a start command followed by an
address byte (R/ W = 1), after which the device acknowledges
that it is prepared to transmit data by pulling SDA low. Two
bytes of data are then read from the device, as shown in
A stop condition follows. If the master does not acknowledge
the first byte, the second byte is not transmitted by the
AD5272/AD5274.
LEAST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
D5
0
D5
0
D4
X
C3
MOST SIGNIFICANT DATA BYTE
D4
MOST SIGNIFICANT DATA BYTE
FRAME 3
FRAME 3
D3
X
C2
D3
FRAME 2
FRAME 2
D2
X
C1
D2
D1
X
C0
D1
AD5272/AD5274
D9
D0
D9
D0
ACK. BY
NO ACK. BY
MASTER
D8
9
D8
9
ACK. BY
MASTER
ACK. BY
AD5272/AD5274
STOP BY
MASTER
STOP BY
MASTER
9
9
Figure 45
.