AD5383BSTZ-5 Analog Devices Inc, AD5383BSTZ-5 Datasheet - Page 11
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AD5383BSTZ-5
Manufacturer Part Number
AD5383BSTZ-5
Description
32-Chn 5V Single Supply 12-Bit Vout I.C.
Manufacturer
Analog Devices Inc
Datasheet
1.AD5383BSTZ-5.pdf
(40 pages)
Specifications of AD5383BSTZ-5
Design Resources
32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015)
Settling Time
6µs
Number Of Bits
12
Data Interface
Serial, Parallel
Number Of Converters
32
Voltage Supply Source
Single Supply
Power Dissipation (max)
65mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD5383BSTZ-5
Manufacturer:
Analog Devices Inc
Quantity:
10 000
PARALLEL INTERFACE TIMING
DV
noted.
Table 8.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
See Figure 7.
See Figure 29.
Measured with the load circuit of Figure 2.
4
4
4, 5
DD
= 2.7 V to 5.5 V; AV
1, 2, 3
Limit at T
4.5
4.5
20
20
0
0
4.5
4.5
20
700
30
670
30
20
100
20
0
100
8
20
35
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
R
= t
R
MIN
= 5 ns (10% to 90% of DV
, T
MAX
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns min
μs max
ns min
μs max
DD
) and timed from a voltage level of 1.2 V.
Rev. B | Page 11 of 40
Description
REG0, REG1, address to WR rising edge setup time
REG0, REG1, address to WR rising edge hold time
CS pulse width low
WR pulse width low
CS to WR falling edge setup time
WR to CS rising edge hold time
Data to WR rising edge setup time
Data to WR rising edge hold time
WR pulse width high
Minimum WR cycle time (single-channel write)
WR rising edge to BUSY falling edge
BUSY pulse width low (single-channel update)
WR rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
LDAC rising edge to WR rising edge
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
MIN
to T
MAX
, unless otherwise
AD5383