AD5522JSVUZ Analog Devices Inc, AD5522JSVUZ Datasheet - Page 54

• Manufacturer Part Number: AD5522JSVUZ
• Description: Quad PPMU With DACs And LVDS/SPI
• Manufacturer: Analog Devices Inc

Specifications of AD5522JSVUZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5522
READBACK OF SYSTEM CONTROL REGISTER
The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 31.
Table 31. System Control Register Readback
Bit
23 (MSB)
22
System Control Register-Specific Readback Bits
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 (LSB)
Bit Name
MODE1
MODE0
CL3
CL2
CL1
CL0
CPOLH3
CPOLH2
CPOLH1
CPOLH0
CPBIASEN
DUTGND/CH
GUARD ALM
CLAMP ALM
INT10K
Guard EN
GAIN1
GAIN0
TMP ENABLE
TMP1
TMP0
Latched
Unused
readback bits
Description
Set the MODE1 and MODE0 bits to 0 to address the system control register.
Read back the status of the individual current clamp enable bits.
0 = clamp is disabled.
1 = clamp is enabled.
When reading back information about the status of the clamp enable function, the data that was most
recently written to the current clamp register from either the system control register or the PMU register
is available in the readback word.
Read back information about the status of the comparator output enable bits.
1 = PMU comparator output is enabled.
0 = PMU comparator output is disabled.
When reading back information about the status of the comparator output enable function, the data
that was most recently written to the comparator status register from either the system control register
or the PMU register is available in the readback word.
This readback bit indicates the status of the comparator enable function.
1 = comparator function is enabled.
0 = comparator function is disabled.
DUTGND per channel enable.
1 = DUTGND per channel is enabled.
0 = individual guard inputs are available per channel.
These bits provide information about which of these alarm bits trigger the CGALM pin.
1 = guard/clamp alarm is enabled.
0 = guard/clamp alarm is disabled.
If this bit is high, the internal 10 kΩ resistor (SW7) is connected between FOHx and MEASVHx, and
between DUTGND and AGND. If this bit is low, SW7 is open.
Read back the status of the guard amplifiers. If this bit is high, the amplifiers are enabled.
Status of the selected MEASOUTx output range. See Table 10 and Table 11.
Read back the status of the thermal shutdown function.
Bits[5:3]
0XX
100
101
110
111
1XX
This bit indicates the status of the open-drain alarm outputs, TMPALM and CGALM.
1 = open-drain alarm outputs are latched.
0 = open-drain alarm outputs are unlatched.
Loads with 0s.
Action
Thermal shutdown disabled.
Thermal shutdown enabled at junction temperature of 130°C (power-on default).
Thermal shutdown enabled at junction temperature of 120°C.
Thermal shutdown enabled at junction temperature of 110°C.
Thermal shutdown enabled at junction temperature of 100°C.
Thermal shutdown enabled.
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