AD5662BRM-1 Analog Devices Inc, AD5662BRM-1 Datasheet - Page 16

• Manufacturer Part Number: AD5662BRM-1
• Description: IC,D/A CONVERTER,SINGLE,16-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5662BRM-1

• Design Resources: 4 mA to 20 mA Process Control Loop Using AD5662 (CN0009) 16-Bit Fully Isolated Voltage Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0063) 16-Bit Fully Isolated 4 mA to 20 mA Output Module Using AD5662, ADuM1401, and External Amplifiers (CN0064)
• Settling Time: 8µs
• Number Of Bits: 16
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 750µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5662
POWER-DOWN MODES
The AD5662 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 5 shows how the state
of the bits corresponds to the device’s mode of operation.
Table 5. Modes of Operation for the AD5662
DB17
0
0
1
1
When both bits are set to 0, the part works normally with its
normal power consumption of 250 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (100 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ or 100 kΩ
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for V
(see Figure 24).
resistor, or left open-circuited (three-state) (see Figure 36).
STRING DAC
RESISTOR
Figure 36. Output Stage During Power-Down
DB16
0
1
0
1
POWER-DOWN
AMPLIFIER
CIRCUITRY
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
DD
= 5 V and for V
RESISTOR
NETWORK
V
DD
OUT
= 3 V
Rev. A | Page 16 of 24
MICROPROCESSOR INTERFACING
AD5662 to Blackfin® ADSP-BF53x Interface
Figure 37 shows a serial interface between the AD5662 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5662, the
setup for the interface is as follows. DT0PRI drives the DIN pin
of the AD5662, while TSCLK0 drives the SCLK of the part. The
SYNC is driven from TFS0.
AD5662 to 68HC11/68L11 Interface
Figure 38 shows a serial interface between the AD5662 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5662, while the MOSI output drives
the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows.
The 68HC11/68L11 is configured with its CPOL bit as a 0 and
its CPHA bit as a 1. When data is being transmitted to the DAC,
the SYNC line is taken low (PC7). When the 68HC11/ 68L11 is
configured as described above, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the AD5662, PC7
is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC; PC7 is taken
high at the end of this procedure.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
68HC11/68L11*
ADSP-BF53x*
Figure 37. AD5662 to Blackfin ADSP-BF53x Interface
Figure 38. AD5662 to 68HC11/68L11 Interface
TSCLK0
DTOPRI
TFS0
MOSI
SCK
PC7
AD5662*
SYNC
DIN
SCLK
AD5662*
SYNC
SCLK
DIN