AD5722RBREZ Analog Devices Inc, AD5722RBREZ Datasheet - Page 28

• Manufacturer Part Number: AD5722RBREZ
• Description: Dual 12Bit DAC 0.5 LSB INL + 10ppm Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5722RBREZ

• Design Resources: Software Configurable 12-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5722R (CN0091)
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 190mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5722R/AD5732R/AD5752R
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 24 and Table 25.
Table 24. Programming the Control Register
MSB
R/W
0
0
0
0
Table 25. Explanation of Control Register Options
Option
NOP
Clear
Load
SDO Disable
CLR Select
Clamp Enable
TSD Enable
Table 26. CLR Select Options
CLR Select Setting
0
1
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power
and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 27 and Table 28.
Table 27. Programming the Power Control Register
MSB
0
Table 28. Power Control Register Functions
Option
PU
PU
PU
TSD
OC
OC
R/W
A
B
REF
A
B
Zero
0
Zero
0
0
0
0
Description
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). After setting this bit to power DAC A, a power-up time of 10 µs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC A powers down automatically on detection of an overcurrent, and PU
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). After setting this bit to power DAC B, a power-up time of 10 µs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC B powers down automatically on detection of an overcurrent, and PU
Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, both DACs are powered down and this bit is set.
DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.
DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.
REG2
0
REG2
0
0
0
0
REG1
1
Description
No operation instruction used in readback operations.
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Addressing this function updates the DAC registers and, consequently, the DAC outputs.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
See Table 26 for a description of the CLR select operation.
Set by the user to enable the current limit clamp. The channel does not power down upon detection of an
overcurrent; the current is clamped at 20 mA (default).
Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent.
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
REG1
1
1
1
1
Unipolar Output Range
0 V
Midscale
REG0
0
REG0
1
1
1
1
A2
0
A2
0
0
1
1
A1
0
A1
0
0
0
0
A0
0
A0
0
1
0
1
DB15
to
DB11
X
DB15 to DB4
Don’t care
Rev. C | Page 28 of 32
DB10
X
DB9
OC
Output CLR Value
B
DB3
TSD enable
DB8
X
DB7
OC
Bipolar Output Range
0 V
Negative full scale
Clear, data = don’t care
Load, data = don’t care
NOP, data = don’t care
A
DB2
Clamp enable
DB6
0
B
A
is cleared to reflect this.
is cleared to reflect this.
DB5
TSD
DB4
PU
REF
DB1
CLR select
DB3
X
DB2
PU
B
LSB
DB0
SDO disable
DB1
X
LSB
DB0
PU
A