AD5724RBREZ-REEL7 Analog Devices Inc, AD5724RBREZ-REEL7 Datasheet - Page 27

• Manufacturer Part Number: AD5724RBREZ-REEL7
• Description: Quad 12Bit DAC 0.5 LSB INL + 10ppm Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5724RBREZ-REEL7

• Design Resources: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DAC REGISTER
The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel which the data transfer
is to take place (see Table 18). The data bits are in positions DB15 to DB0 for the AD5754R (see Table 19), DB15 to DB2 for the AD5734R
(see Table 20), and DB15 to DB4 for the AD5724R (see Table 21).
Table 19. Programming the AD5754R DAC Register
MSB
R/ W
0
Table 20. Programming the AD5734R DAC Register
MSB
R/ W
0
Table 21. Programming the AD5724R DAC Register
MSB
R/ W
0
OUTPUT RANGE SELECT REGISTER
The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, while the
range bits (R2, R1, R0) select the required output range (see Table 22 and Table 23).
Table 22. Programming the Required Output Range
MSB
R/ W
1/0
Table 23. Output Range Options
R2
0
0
0
0
1
1
Zero
0
Zero
0
Zero
0
Zero
0
REG2
0
REG2
0
R1
0
0
1
1
0
0
REG2
0
REG2
0
REG1
0
REG1
0
REG1
0
REG0
1
REG0
0
R0
0
1
0
1
0
1
REG1
0
REG0
0
A2
A2
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DAC address
REG0
0
DAC address
A1
A2
A1
Output Range (V)
+5
+10
+10.8
±5
±10
±10.8
A0
DAC address
A1
A0
A2
DB15 to DB3
Don’t care
DB15 to DB4
12-bit DAC data
A0
DAC address
AD5724R/AD5734R/AD5754R
A1
DB15 to DB2
14-bit DAC data
DB2
R2
A0
DB3
X
DB1
R1
DB2
X
DB15 to DB0
16-bit DAC data
DB1
X
DB1
X
DB0
R0
DB0
X
DB0
X
LSB
LSB
LSB
LSB