AD5781ARUZ-REEL7 Analog Devices Inc, AD5781ARUZ-REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD5781ARUZ-REEL7
• Description: 18bit, 4LSB, Unbuffered Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5781ARUZ-REEL7

• Design Resources: 18-Bit Accurate, low noise, precision bipolar DC voltage source (CN0177)
• Settling Time: 1µs
• Number Of Bits: 18
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
V
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
All input signals are specified with t
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
2
CC
= 2.7 V to 5.5 V; all specifications T
IOV
40
92
15
9
5
2
48
8
9
12
13
20
14
130
10
130
50
140
0
65
62
0
35
150
CC
= 1.71 V to 3.3 V
R
= t
F
= 1 ns/V (10% to 90% of IOV
Limit
MIN
1
IOV
28
60
10
5
5
2
40
6
7
7
10
16
11
130
10
130
50
140
0
60
45
0
35
150
to T
CC
MAX
= 3.3 V to 5.5 V
, unless otherwise noted.
CC
) and timed from a voltage level of (V
Rev. 0 | Page 5 of 28
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
μs typ
ns typ
ns min
ns typ
ns min
ns max
ns max
ns min
ns typ
ns typ
Test Conditions/Comments
SCLK cycle time
SCLK cycle time (readback and daisy-chain modes)
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge hold time
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignore
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to output response time
Output settling time (20 V step)
SYNC rising edge to output response time (LDAC tied low)
CLR pulse width low
CLR pulse activation time
SYNC falling edge to first SCLK rising edge
SYNC rising edge to SDO tristate (C
SCLK rising edge to SDO valid (C
SYNC rising edge to SCLK rising edge ignore
RESET pulse width low
RESET pulse activation time
IL
+ V
IH
)/2.
L
= 50 pF)
L
= 50 pF)
AD5781