AD6636BBCZ Analog Devices Inc, AD6636BBCZ Datasheet - Page 75

• Manufacturer Part Number: AD6636BBCZ
• Description: IC,Downconverter,CMOS,BGA,256PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636BBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

<3:0>: Stream Control Bits. These bits are described in Table 46.
Table 46. Stream Control Bits
Stream
Control Bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Default
AGC0, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC0. Note that AGC0 may be bypassed, and that
AGC0 here is representative of the datapath only.
AGC0, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC0. Note that AGC0 may be bypassed,
and that AGC0 here is representative of the datapath only.
AGC1, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC1. Note that AGC1 may be bypassed and that
AGC1 here is representative of the datapath only.
AGC1, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC1. Note that AGC1 may be bypassed
and that AGC1 here is representative of the datapath only.
AGC2, I Output <15:0:
This read-only register provides the latest in-phase output
sample from AGC2. Note that AGC2 may be bypassed and that
AGC2 here is representative of the datapath only.
Output Streams (str0, str1,
str2, str3, str4, str5)
Ch 0/Ch 1 combined; Ch 2, Ch 3,
Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2 combined; Ch 3,
Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3 combined;
Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3/Ch 4 combined;
Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3/Ch 4/Ch 5
Ch 0/Ch 1/Ch 2 combined,
Ch 3/Ch 4/Ch 5 combined
Ch 0/Ch 1 combined, Ch 2/Ch 3
combined, Ch 4/Ch 5 combined
Ch 0/Ch 1 combined, Ch 2/Ch 3
combined, Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2 combined, Ch 3/Ch 4
combined, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3 combined,
Ch 4/Ch 5 combined.
Independent channels
combined
No. of
Streams
5
4
3
2
1
2
3
4
3
2
6
Rev. A | Page 75 of 80
AGC2, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC2. Note that AGC2 may be bypassed
and that AGC2 here is representative of the datapath only.
AGC3, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC3. Note that AGC3 may be bypassed and that
AGC3 here is representative of the datapath only.
AGC3, Q output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC3. Note that AGC3 may be bypassed
and that AGC3 here is representative of the datapath only.
AGC4, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC4. Note that AGC4 may be bypassed and that
AGC4 here is representative of the datapath only.
AGC4, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC4. Note that AGC4 may be bypassed
and that AGC4 here is representative of the datapath only.
AGC5, I Output <15:0>
This read-only register provides the latest in-phase output
sample from AGC5. Note that AGC5 may be bypassed and that
AGC5 here is representative of the datapath only.
AGC5, Q Output <15:0>
This read-only register provides the latest quadrature-phase
output sample from AGC5. Note that AGC5 may be bypassed
and that AGC5 here is representative of the datapath only.
AGC0, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC0. This register is updated only when AGC0 is
enabled and operating.
AGC1, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC1. This register is updated only when AGC1 is
enabled and operating.
AGC2, RSSI Output <11:0>
This read-only register provides the latest RSSI output sample
from AGC2. This register is updated only when AGC2 is
enabled and operating.
AD6636