AD7265BCPZ-REEL7 Analog Devices Inc, AD7265BCPZ-REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD7265BCPZ-REEL7
• Description: IC,Data Acquisition System,3-CHANNEL,12-BIT,LLCC,32PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7265BCPZ-REEL7

• Design Resources: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 21mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7265CB - BOARD EVALUATION FOR AD7265
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
AV
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial
Interface section and Figure 41 and Figure 42.
Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.
The time required for the output to cross 0.4 V or 2.4 V.
3
DD
2
= DV
DD
= 2.7 V to 5.25 V, V
Limit at T
1
4
16
14 × t
875
30
15/20
20/30
15
36
27
0.45 t
0.45 t
10
5
15
30
5
50
SCLK
SCLK
SCLK
MIN
, T
MAX
DRIVE
= 2.7 V to 5.25 V, internal/external reference = 2.5 V, T
Unit
MHz min
MHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
Rev. A | Page 5 of 28
Description
T
T
t
f
Minimum time between end of serial read and next falling edge of CS
V
V
Delay from CS until D
Data access time after SCLK falling edge, V
Data access time after SCLK falling edge, V
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time, V
SCLK to data valid hold time, V
CS rising edge to D
CS rising edge to falling edge pulse width
SCLK falling edge to D
SCLK falling edge to D
SCLK
SCLK
A
A
DD
DD
= −40°C to +85°C
> 85°C to 125°C
= 5 V/3 V, CS to SCLK setup time, T
= 5 V/3 V, CS to SCLK setup time, T
= 1/f
= 16 MHz
SCLK
OUT
OUT
A, D
OUT
OUT
A and D
A, D
A, D
OUT
B, high impedance
OUT
OUT
DD
DD
A
B, high impedance
B, high impedance
OUT
= T
= 3 V
= 5 V
B are three-state disabled
MAX
A
A
= −40°C to +85°C
> 85°C to 125°C
DD
to T
) and timed from a voltage level of 1.6 V.
DD
DD
MIN
= 3 V
= 5 V
, unless otherwise noted
AD7265
1
.