AD7294BSUZRL Analog Devices Inc, AD7294BSUZRL Datasheet - Page 34

• Manufacturer Part Number: AD7294BSUZRL
• Description: IC,Data Acquisition System,4-CHANNEL,12-BIT,TQFP,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: ADC, DACr

Specifications of AD7294BSUZRL

• Resolution (bits): 12 b
• Sampling Rate (per Second): 22.22k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7294
I
GENERAL I
Figure 50 shows the timing diagram for general read and write
operations using an I
The I
is driving the bus, both SCL and SDA are high. This is known as
idle state. When the bus is idle, the master initiates a data transfer
by establishing a start condition, defined as a high-to-low
transition on the serial data line (SDA) while the serial clock line
(SCL) remains high. This indicates that a data stream follows. The
master device is responsible for generating the clock.
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter followed by an acknowledge bit (ACK)
from the receiver. Data transitions on the SDA line must occur
during the low period of the clock signal and remain stable
during the high period. The receiver should pull the SDA line
low during the acknowledge bit to signal that the preceding byte
has been received correctly. If this is not the case, cancel the
transaction.
The first byte that the master sends must consist of a 7-bit slave
address, followed by a data direction bit. Each device on the bus
has a unique slave address; therefore, the first byte sets up
2
C INTERFACE
2
C bus uses open-drain drivers; therefore, when no device
SDA
SCL
START COND
BY MASTER
2
C TIMING
A6
2
C-compliant interface.
SLAVE ADDRESS BYTE
A5
USER PROGRAMMABLE 5 LSBs
A4
A3
A2
A1
A0
Figure 50. General I
R/W
ACK. BY
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AD7294
P7
2
C Timing
communication with a single slave device for the duration of the
transaction.
The transaction can be used either to write to a slave device
(data direction bit = 0) or to read data from it (data direction
bit = 1). In the case of a read transaction, it is often necessary
first to write to the slave device (in a separate write transaction)
to tell it from which register to read. Reading and writing
cannot be combined in one transaction.
When the transaction is complete, the master can keep control
of the bus, initiating a new transaction by generating another
start bit (high-to-low transition on SDA while SCL is high). This
is known as a repeated start (Sr). Alternatively, the bus can be
relinquished by releasing the SCL line followed by the SDA line.
This low-to-high transition on SDA while SCL is high is known
as a stop bit (P), and it leaves the I
current is consumed by the bus).
The example in Figure 50 shows a simple write transaction
with an AD7294 as the slave device. In this example, the
AD7294 register pointer is being set up ready for a future read
transaction.
P6
P5
REGISTER ADDRESS
P4
P3
P2
P1
2
P0
C bus in its idle state (no
ACK. BY
AD7294
STOP BY
MASTER