AD73311LARUZ-RL Analog Devices Inc, AD73311LARUZ-RL Datasheet - Page 27
![SINGLE-CHANNEL AFE I.C.](/photos/1/38/13835/505-20-ssop_sml.jpg)
AD73311LARUZ-RL
Manufacturer Part Number
AD73311LARUZ-RL
Description
SINGLE-CHANNEL AFE I.C.
Manufacturer
Analog Devices Inc
Datasheet
1.AD73311ARZ.pdf
(36 pages)
Specifications of AD73311LARUZ-RL
Number Of Bits
16
Number Of Channels
2
Power (watts)
50mW
Voltage - Supply, Analog
3V
Voltage - Supply, Digital
3V
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Good decoupling is important when using high speed devices.
All analog and digital supplies should be decoupled to AGND
and DGND respectively, with 0.1 µF ceramic capacitors in
parallel with 10 µF tantalum capacitors. To achieve the best
from these decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against it. In systems
where a common supply voltage is used to drive both the AVDD
and DVDD of the AD73311, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD73311 and AGND and the recommended digital
supply decoupling capacitors between the DVDD pin and
DGND.
DSP Programming Considerations
This section discusses some aspects of how the serial port of the
DSP should be configured and the implications of whether Rx
and Tx interrupts should be enabled.
DSP SPORT Configuration
Following are the key settings of the DSP SPORT required for
the successful operation with the AD73311:
• Configure for external SCLK.
• Serial Word Length = 16 bits.
• Transmit and Receive Frame Syncs required with every word.
• Receive Frame Sync is an input to the DSP.
• Transmit Frame Sync is an:
• Frame Syncs occur one SCLK cycle before the MSB of the
•
• Frame Syncs are active high.
serial word.
Input—in Frame Sync Loop-Back Mode
Output—in Nonframe Sync Loop-Back Mode.
DSP SPORT Interrupts
If SPORT interrupts are enabled, it is important to note that the
active signals on the frame sync pins do not necessarily corre-
spond with the positions in time of where SPORT interrupts are
generated.
On ADSP-21xx processors, it is necessary to enable SPORT
interrupts and use Interrupt Service Routines (ISRs) to handle
Tx/Rx activity, while on the TMS320CSx processors it is pos-
sible to poll the status of the Rx and Tx registers, which means
that Rx/Tx activity can be monitored using a single ISR that
would ideally be the Tx ISR as the Tx interrupt will typically
occur before the Rx ISR.
AD73311