AD7352BRUZ-RL Analog Devices Inc, AD7352BRUZ-RL Datasheet - Page 18

• Manufacturer Part Number: AD7352BRUZ-RL
• Description: 12-Bit Dual Diff Simult 3 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7352BRUZ-RL

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040)
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 45mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7352
SERIAL INTERFACE
Figure 30 shows the detailed timing diagram for serial
interfacing to the AD7352. The serial clock provides the
conversion clock and controls the transfer of information
from the AD7352 during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 SCLKs to complete. Once
13 SCLK falling edges have elapsed, the track and hold goes
back into track on the next SCLK rising edge, as shown in
Figure 30
AD7352, then two trailing zeros appear after the final LSB. On
the rising edge of
and SDATA
but is instead held low for an additional 14 SCLK cycles, the
data from the conversion on ADC B is output on SDATA
Figure 31
SDATA
). Likewise, the data from the conversion on ADC A is
at Point B. If a 16-bit data transfer is used on the
SDATA
SDATA
SCLK
B
SCLK
CS
go back into three-state. If
A
CS
THREE-
STATE
A
B
THREE-
STATE
CS , the conversion is terminated and SDATA
t
2
2 LEADING
0
2 LEADING ZEROS
ZEROS
t
1
2
0
t
3
0
1
t
3
0
2
DB11
2
A
DB11
Figure 31. Reading Data from Both ADCs on One SDATA Line with 32 SCLKs
3
DB10
CS is not brought high,
A
3
DB10
4
DB9
t
t
6
A
4
Figure 30. Serial Interface Timing Diagram
4
t
5
5
DB9
t
t
6
4
A
t
CONVERT
(see
2 TRAILING ZEROS
5
t
14
7
Rev. 0 | Page 18 of 20
ZERO
DB8
A
t
7
15
ZERO
2 LEADING ZEROS
output on SDATA
back into three-state on the 32
edge of
A minimum of 14 serial clock cycles is required to perform
the conversion process and to access data from one conversion
on either data line of the AD7352. CS falling low provides the
leading zero to be read in by the microcontroller or DSP. The
remaining data is then clocked out by subsequent SCLK falling
edges, beginning with a second leading zero. Thus, the first falling
clock edge on the serial clock has the leading zero provided and
also clocks out the second leading zero. The 12-bit result then
follows with the final bit in the data transfer and is valid on the
14
falling edge). In applications with a slower SCLK, it may be
possible to read in data on each SCLK rising edge, depending
on the SCLK frequency. With a slower SCLK, the first rising
edge of SCLK after the CS falling edge has the second leading
zero provided, and the 13
16
ZERO
th
DB2
falling edge (having been clocked out on the previous (13
17
CS , whichever occurs first.
ZERO
t
5
DB1
DB11
13
B
. In this case, the SDATA line in use goes
B
B
t
DB0
8
th
rising SCLK edge has DB0 provided.
t
ACQUISITION
ZERO
THREE-STATE
2 TRAILING ZEROS
nd
SCLK falling edge or the rising
t
QUIET
ZERO
t
9
32
t
10
THREE-
STATE
th
)