AD7356BRUZ Analog Devices Inc, AD7356BRUZ Datasheet - Page 17

• Manufacturer Part Number: AD7356BRUZ
• Description: 12-Bit Dual Diff Simult 5 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7356BRUZ

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7356 (CN0041)
• Number Of Bits: 12
• Sampling Rate (per Second): 3M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 59mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER-UP TIMES
The AD7356 has two power-down modes: partial power-down
and full power-down, which are described in detail in the Normal
Mode, Partial Power-Down Mode, and Full Power-Down Mode
sections. This section deals with the power-up time required
when coming out of any of these modes. Note that the recom-
mended decoupling capacitors must be in place on the REF
and REF
To power up from partial power-down mode, one dummy cycle
is required. The device is fully powered up after approximately
200 ns have elapsed from the falling edge of CS . When the
partial power-up time has elapsed, the ADC is fully powered
up, and the input signal is acquired properly. The quiet time,
t
back into three-state after the dummy conversion to the next
falling edge of CS .
To power up from full power-down mode, approximately 6 ms
should be allowed from the falling edge of CS , shown in
Figure 28
Note that during power-up from partial power-down mode, the
track-and-hold, which is in hold mode while the part is powered
down, returns to track mode after the first SCLK edge that the
part receives after the falling edge of CS .
When power supplies are first applied to the AD7356, the ADC
can power up in either of the power-down modes or in normal
mode. Because of this, it is best to allow a dummy cycle to elapse
to ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the part is to be kept in partial
power-down mode immediately after the supplies are applied,
then two dummy cycles must be initiated. The first dummy
cycle must hold CS low until after the 10
the second cycle, CS must be brought high between the second
and 10
QUIET
, must still be allowed from the point where the bus goes
th
SCLK falling edges (see
B
as t
pins for the power-up times to apply.
POWER-UP2
.
Figure 25
th
).
SCLK falling edge; in
A
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Alternatively, if the part is to be placed into full power-down
mode when the supplies are applied, three dummy cycles must
be initiated. The first dummy cycle must hold CS low until after
the 10
place the part into full power-down mode (see
the
POWER vs. THROUGHPUT RATE
The power consumption of the AD7356 varies with the
throughput rate. When using very slow throughput rates
and as fast an SCLK frequency as possible, the various power-
down options can be used to make significant power savings.
However, the AD7356 quiescent current is low enough that
even without using the power-down options, there is a noticeable
variation in power consumption with sampling rate. This is true
whether a fixed SCLK value is used or it is scaled with the
sampling rate. Figure 29 shows a plot of power vs. throughput rate
when operating in normal mode for a fixed maximum SCLK
frequency and a SCLK frequency that scales with the sampling
rate. The internal reference was used for Figure 29.
Modes of Operation
th
SCLK falling edge; the second and third dummy cycles
38
34
30
26
22
18
14
10
0
80MHz SCLK
Figure 29. Power vs. Throughput Rate
1000
section).
THROUGHPUT (kSPS)
2000
VARIABLE SCLK
3000
Figure 27
4000
AD7356
5000
and