AD7357BRUZ-RL Analog Devices Inc, AD7357BRUZ-RL Datasheet - Page 12

• Manufacturer Part Number: AD7357BRUZ-RL
• Description: 14-Bit Dual Diff Simult 5 MSPS ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7357BRUZ-RL

• Design Resources: DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7357 (CN0061)
• Number Of Bits: 14
• Sampling Rate (per Second): 4.2M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 59mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7357
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7357 is a high speed, dual, 14-bit, single-supply, successive
approximation analog-to-digital converter. The part operates
from a 2.5 V power supply and features throughput rates up to
4.2 MSPS.
The AD7357 contains two on-chip differential track-and-hold
amplifiers, two successive approximation analog-to-digital
converters, and a serial interface with two separate data output
pins. The part is housed in a 16-lead TSSOP package, offering
the user considerable space-saving advantages over alternative
solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The AD7357 has an on-chip 2.048 V reference. If an
external reference is desired the internal reference can be
overdriven with a reference value ranging from (2.048 V +
100 mV) to V
where in the system, the reference output needs to be buffered
first. The differential analog input range for the AD7357 is V
± V
The AD7357 features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described
in the Modes of Operation section.
CONVERTER OPERATION
The AD7357 has two successive approximation ADCs, each
based around two capacitive DACs. Figure 14 and Figure 15
show simplified schematics of one of these ADCs in acquisition
and conversion phases, respectively. The ADC comprises
control logic, a SAR, and two capacitive DACs. In Figure 14
(the acquisition phase), SW3 is closed, SW1 and SW2 are in
Position A, the comparator is held in a balanced condition,
and the sampling capacitor arrays may acquire the differential
signal on the input.
When the ADC starts a conversion (see Figure 15), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
REF
/2.
V
V
IN+
IN–
B
A
A
B
V
DD
REF
SW1
SW2
. If the internal reference is to be used else-
Figure 14. ADC Acquisition Phase
C
C
S
S
SW3
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
DAC
DAC
LOGIC
Rev. A | Page 12 of 20
CM
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of
the sources driving the V
otherwise, the two inputs have different settling times, resulting
in errors.
ANALOG INPUT STRUCTURE
Figure 16 shows the equivalent circuit of the analog input struc-
ture of the AD7357. The four diodes provide ESD protection for
the analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than 300 mV.
Exceeding the limit causes these diodes to become forward-
biased and start conducting into the substrate. These diodes
can conduct up to 10 mA without causing irreversible damage
to the part.
The C1 capacitors in Figure 16 are typically 8 pF and can
primarily be attributed to pin capacitance. The R1 resistors
are lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 30 Ω.
The C2 capacitors are the ADC’s sampling capacitors with a
capacitance of 32 pF typically.
Conversion Phase—Switches Open, Track Phase—Switches Closed
V
V
IN+
IN–
B
B
A
A
V
REF
Figure 16. Equivalent Analog Input Circuit,
SW1
SW2
V
V
IN+
IN–
Figure 15. ADC Conversion Phase
C1
C1
C
C
S
S
IN+
V
V
DD
DD
and V
D
D
D
D
SW3
COMPARATOR
IN−
pins must be matched;
R1 C2
R1 C2
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC