AD7376ARWZ10-RL Analog Devices Inc, AD7376ARWZ10-RL Datasheet - Page 14

• Manufacturer Part Number: AD7376ARWZ10-RL
• Description: IC,Digital Potentiometer,CMOS,SOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7376ARWZ10-RL

• Taps: 128
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 33 V, ±4.5 V ~ 16.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7376EBZ - BOARD EVAL FOR AD7376
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7376
DAISY-CHAIN OPERATION
Figure 27 shows the details of the serial data output pin (SDO).
SDO shifts out the SDI content in the previous frame; therefore,
it can be used for daisy-chaining multiple devices. The SDO pin
contains an open-drain N-Channel MOSFET and requires a
pull-up resistor if the SDO function is used.
Users need to tie the SDO pin of one package to the SDI pin of
the next package. For example, in Figure 28, if two AD7376s are
daisy-chained, a total of 14 bits of data are required for each
operation. The first set of seven bits goes to U2; the second set
of seven bits goes to U1. CS should be kept low until all 14 bits
are clocked into their respective serial registers. Then CS is
pulled high to complete the operation.
When daisy-chaining multiple devices, users may need to
increase the clock period because the pull-up resistor and the
capacitive loading at the SDO to SDI interface may induce a
time delay to subsequent devices.
SCLK
µC
SHDN
CLK
MOSI
SDI
CS
RS
SS
Figure 27. Detailed SDO Output Schematic of the AD7376
REGISTER
SERIAL
SDI
Figure 28. Daisy-Chain Configuration
CS
AD7376
U1
CLK
SDO
D
CK
RS
Q
V
DD
R
2.2kΩ
PU
SDI
CS
AD7376
U2
CLK
SDO
SDO
Rev. C | Page 14 of 20
ESD PROTECTION
All digital inputs are protected with a series input resistor and
an ESD structure shown in Figure 29. These structures apply to
digital input pins CS , CLK, SDI, RS , and SHDN .
All analog terminals are also protected by ESD protection
diodes, as shown in Figure 30.
TERMINAL VOLTAGE OPERATING RANGE
The AD7376 V
conditions for proper 3-terminal digital potentiometer oper-
ation. Applied signals present on Terminals A, B, and W that
are more positive than V
clamped by the internal forward-biased diodes (see Figure 30).
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminals A, B, and W (see Figure 30), it is
important to power V
Terminals A, B, and W. Otherwise, the diodes are forward
biased such that V
the system. Similarly, V
The ideal power-up sequence is in the following order: GND,
V
V
they are powered after V
DD
A
, V
, V
B
, V
SS
, digital inputs, and V
W
, and the digital inputs is not important, as long as
Figure 30. Equivalent ESD Protection Analog Pins
Figure 29. Equivalent ESD Protection Circuit
LOGIC
DD
PINS
and V
DD
/V
DD
SS
DD
SS
/V
DD
DD
are powered unintentionally and affect
/V
power supplies define the boundary
SS
/V
or more negative than V
SS
before applying voltage to
SS
A
INPUT
should be powered down last.
340Ω
/V
.
B
/V
W
. The order of powering
GND
V
DD
V
V
A
W
B
SS
DD
SS
will be