AD7685ARMZ Analog Devices Inc, AD7685ARMZ Datasheet - Page 17

• Manufacturer Part Number: AD7685ARMZ
• Description: IC,A/D CONVERTER,SINGLE,16-BIT,CMOS,TSSOP,10PIN
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7685ARMZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: SAR
• Sample Rate: 250KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 5.8V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 2.5/3.3/5V
• Single Supply Voltage (min): 2.3V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 15mW
• Integral Nonlinearity Error: ±6LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 10
• Package Type: MSOP
• Input Signal Type: Pseudo-Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7685CBZ - BOARD EVAL FOR AD7685
• Lead Free Status / Rohs Status: Compliant

The AD7685 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 32. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7685, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 33. The reference line can be driven by either:
• The system power supply directly.
• A reference voltage with enough current output capability,
• A reference buffer, such as the AD8031, that can also filter
such as the ADR43x.
the system power supply, as shown in Figure 33.
10000
0.001
1
1000
0.01
5V
OPTIONAL REFERENCE BUFFER AND FILTER.
100
0.1
10
1
10
10kΩ
1µF
Figure 32. Operating Currents vs. Sampling Rate
Figure 33. Example of Application Circuit
100
5V
AD8031
SAMPLING RATE (SPS)
1000
1
10µF
VIO
5V
10000
VDD = 5V
REF
10Ω
100000
AD7685
VDD
VDD = 2.5V
1µF
1000000
VIO
Rev. B | Page 17 of 28
DIGITAL INTERFACE
Though the AD7685 has a reduced number of pins, it offers
substantial flexibility in its serial interface modes.
The AD7685, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals minimizes
wiring connections, useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.
The AD7685, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either the CS mode or the chain mode, the AD7685 offers the
flexibility to optionally force a start bit in front of the data bits.
This start bit can be used as a BUSY signal indicator to
interrupt the digital host and trigger the data reading.
Otherwise, without a BUSY indicator, the user must time out
the maximum conversion time prior to readback.
The BUSY indicator feature is enabled as follows:
• In the CS mode, if CNV or SDI is low when the ADC
• In the chain mode, if SCK is high during the CNV rising edge
conversion ends (see Figure 37 and Figure 41).
(see Figure 45).
AD7685