AD7718BR Analog Devices Inc, AD7718BR Datasheet - Page 9

• Manufacturer Part Number: AD7718BR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc

Specifications of AD7718BR

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 24 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Features: Analog Front End For Low Frequency Measurement
• No. Of Channels: 10
• Rohs Status: RoHS non-compliant
• Number Of Bits: 24
• Sampling Rate (per Second): 1.37k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 3.84mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD7718EBZ - BOARD EVALUATION FOR AD7718
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TIMING CHARACTERISTICS
DGND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV
Parameter
t
t
Read Operation
Write Operation
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
level of 1.6 V.
See Figures 1 and 2.
SCLK active edge is falling edge of SCLK.
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
This specification only comes into play if CS goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the load circuit of Figure 1. The measured number is
then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true
bus relinquish times of the part and as such are independent of external bus loading capacitances.
RDY returns high after the first read from the device after an output update. The same data can be read again, if required, while RDY is high, although care should
be taken that subsequent reads do not occur close to the next output update.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
4
5
5A
6
7
8
9
10
11
12
13
14
15
16
4
6
4, 5
Limit at T
(B Version)
32.768
50
0
0
0
60
80
0
60
80
100
100
0
10
80
100
0
30
25
100
100
0
1, 2
MIN
TO OUTPUT
, T
(AV
MAX
DD
PIN
= 2.7 V to 3.6 V or AV
50pF
Unit
kHz typ
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
DD
unless otherwise noted.
I
I
(200 A WITH DV
100 A WITH DV
SINK
SOURCE
DD
100 A WITH DV
(1.6mA WITH DV
= 5 V
1.6V
Conditions/Comments
Crystal Oscillator Frequency
RESET Pulsewidth
RDY to CS Setup Time
CS Falling Edge to SCLK Active Edge Setup Time
SCLK Active Edge to Data Valid Delay
DV
DV
CS Falling Edge to Data Valid Delay
DV
DV
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Inactive Edge Hold Time
Bus Relinquish Time after SCLK Inactive Edge
SCLK Active Edge to RDY High
CS Falling Edge to SCLK Active Edge Setup Time
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Edge Hold Time
DD
DD
5%; DV
= 3V)
DD
DD
DD
DD
= 5V
DD
DD
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 3V)
= 5V
DD
= 2.7 V to 3.6 V or DV
OL
or V
DD
AD7708/AD7718
) and timed from a voltage
OH
limits.
DD
= 5 V
3, 7
3
3
5%; AGND =
3
3
3
3