AD7863ARZ-2 Analog Devices Inc, AD7863ARZ-2 Datasheet - Page 5

• Manufacturer Part Number: AD7863ARZ-2
• Description: IC,Data Acquisition System,2-CHANNEL,14-BIT,SOP,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7863ARZ-2

• Number Of Bits: 14
• Sampling Rate (per Second): 175k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 94.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
V
Table 2.
Parameter
t
t
Parallel Interface
1
2
3
4
CONV
ACQ
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figure 2.
Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V.
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
DD
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
3
4
= 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
1, 2
CONVST
BUSY
DATA
RD
CS
A0
A, B Versions
5.2
0.5
0
0
35
45
30
5
30
10
400
t
CONV
t
3
= 5.2µs
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
t
1
t
5
TO OUTPUT
t
V
4
A1
PIN
Figure 2. Timing Diagram
Rev. B | Page 5 of 24
V
A2
t
ACQ
50pF
t
8
Unit
μs max
μs max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
t
6
t
2
MIN
1.6mA
200µA
to T
MAX
, unless otherwise noted.
V
B1
t
7
Test Conditions/Comments
Conversion time
Acquisition time
CS to RD setup time
CS to RD hold time
CONVST pulse width
RD pulse width
Data access time after falling edge of RD
Bus relinquish time after rising edge of RD
Time between consecutive reads
Quiet time
V
B2
AD7863