AD7899ARZ-1 Analog Devices Inc, AD7899ARZ-1 Datasheet - Page 6

• Manufacturer Part Number: AD7899ARZ-1
• Description: 14-BIT BIPOLAR INPUT SINGLE SUPPLY ADC
• Manufacturer: Analog Devices Inc

Specifications of AD7899ARZ-1

• Rohs Compliant: YES
• Number Of Bits: 14
• Sampling Rate (per Second): 400k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 125mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7899CBZ - BOARD EVAL FOR AD7899
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7899
Pin
No.
1
2, 6
3, 4
5
7–13
14
15
16–22
23
24
25
26
27
28
Mnemonic
V
GND
V
V
DB13–DB7
OPGND
V
DB6–DB0
BUSY/EOC
RD
CS
CONVST
CLKIN
STBY
REF
INB
DD
DRIVE
, V
INA
Description
Reference Input/Output. This pin is provides access to the internal reference (2.5 V ± 20 mV) and
also allows the internal reference to be overdriven by an external reference source (2.5 V ± 5%).
A 0.1 µF decoupling capacitor should be connected between this pin and GND.
Ground Pin. This pin should be connected to the system’s analog ground plane.
Analog Inputs. See Analog Input Section.
Positive Supply Voltage, 5.0 V ± 5%.
Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 7. Three-state outputs.
Output Driver Ground. This is the ground pin of the output drivers for D13 to D0 and BUSY/EOC. It should
be connected to the system’s analog ground plane .
This pin provides the positive supply voltage for the digital inputs and outputs. It is normally tied to V
but may also be powered by a 3 V ± 10% supply which allows the inputs and outputs to be interfaced
to 3 V processors and DSPs. V
Data Bit 6 to Data Bit 0. Three-state Outputs.
BUSY/EOC Output. Digital output pin used to signify that a conversion is in progress or that a conversion
has finished. The function of the BUSY/EOC is determined by the state of CONVST at the end of con-
version. See the Timing and Control Section.
Read Input. Active low logic input which is used in conjunction with CS low to enable the data outputs.
Chip Select Input. Active low logic input. The device is selected when this input is active.
Convert Start Input. Logic Input. A low to high transition on this input puts the track/hold into hold mode
and starts conversion.
Conversion Clock Input. CLKIN is an externally applied clock which allows the user to control the
conversion rate of the AD7899. If the CLKIN input is high on the rising edge of CONVST an externally
applied clock will be used as the conversion clock. If the CLKIN is low on the rising edge of CONVST
the internal laser-trimmed oscillator is used as the conversion clock. Each conversion needs sixteen clock
cycles in order for the conversion to be completed. The externally applied clock should have a duty cycle
no greater than 60/40. The CLKIN pin can be tied to GND if an external clock is not required.
Standby Mode Input. Logic input which is used to put the device into the power save or standby mode.
The STBY input is high for normal operation and low for standby operation.
PIN FUNCTION DESCRIPTIONS
OPGND
PIN CONFIGURATION
DB13
DB12
DB11
DB10
V
GND
GND
V
V
DB9
DB8
DB7
V
REF
INB
INA
DRIVE
DD
10
11
12
13
14
SOIC/SSOP
1
2
3
4
5
6
7
8
9
(Not to Scale)
should be decoupled with a 0.1 µF capacitor to GND.
TOP VIEW
AD7899
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STBY
CLKIN
CONVST
CS
RD
BUSY/EOC
DB0
DB1
DB2
DB3
DB4
DB5
V
DB6
DRIVE
DD