AD8253ARMZ-RL Analog Devices Inc, AD8253ARMZ-RL Datasheet - Page 17

• Manufacturer Part Number: AD8253ARMZ-RL
• Description: IC,Instrumentation Amplifier,SINGLE,CMOS,TSSOP,10PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: iCMOS®r

Specifications of AD8253ARMZ-RL

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 20 V/µs
• -3db Bandwidth: 10MHz
• Current - Input Bias: 5nA
• Voltage - Input Offset: 150µV
• Current - Supply: 4.6mA
• Current - Output / Channel: 37mA
• Voltage - Supply, Single/dual (±): ±5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
−V
−V
−V
−V
Latched Gain Mode
Some applications have multiple programmable devices such
as multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using WR as a latch,
allowing other devices to share A0 and A1.
schematic using this method, known as latched gain mode. The
AD8253 is in this mode when
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the WR signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table listing
in
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
Table 6
S
S
S
S
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 1000.
–IN
+IN
10μF
10μF
for more on these gain changes.
Figure 53. Latched Gain Mode, G = 1000
0.1µF
0.1µF
A1
Low
Low
High
High
+15V
–15V
+
–
AD8253
DGND
WR
A1
WR is held at logic high or logic
A0
Low
High
Low
High
A0
REF
G = PREVIOUS
STATE
DGND
WR
A1
A0
A0, A1
WR
Figure 53
G = 1000
Gain
1
10
100
1000
+5V
0V
+5V
0V
+5V
0V
Figure 54. Timing Diagram for Latched Gain Mode
shows a
t
WR-HIGH
Rev. A | Page 17 of 24
t
SU
t
HD
t
WR-LOW
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
High to Low
High to Low
High to Low
High to Low
Low to Low
Low to High
High to High
1
On power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 on power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, t
latches in the gain. Similarly, they must be held for a minimum
hold time, t
the gain is latched in correctly. After t
logic levels, but the gain does not change until the next downward
edge of WR . The minimum duration that WR can be held high
is t
be held low. Digital timing specifications are listed in
The time required for a gain change is dominated by the settling
time of the amplifier. A timing diagram is shown in
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
X = don’t care.
WR
-HIGH
, and t
HD
, after the downward edge of WR to ensure that
WR
-LOW
A1
Low
Low
X
X
X
High
High
1
1
1
is the minimum duration that WR can
SU
, before the downward edge of WR
A0
Low
High
Low
High
X
X
X
1
1
1
HD
Gain
Change to 1
Change to 10
Change to 100
Change to 1000
No change
No change
No change
, A0 and A1 may change
AD8253
Figure 54
Table 2.
.