AD8304ARUZ-RL7 Analog Devices Inc, AD8304ARUZ-RL7 Datasheet - Page 10

• Manufacturer Part Number: AD8304ARUZ-RL7
• Description: IC,Level Detector,TSSOP,14PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Logarithmic Converterr

Specifications of AD8304ARUZ-RL7

• Design Resources: Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
• Applications: Fiber Optics
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8304
Using a value of 0.3 pF for C
fore, the minimum bandwidth at I
While this simple model is useful in making a point, it excludes
other effects that limit its usefulness. For example, the network
R1, C1 in Figure 1, which is necessary to stabilize the system over
the full range of currents, affects bandwidth at all values of I
Later signal processing blocks also limit the maximum value.
TPC 7 shows ac response curves for the AD8304 at eight repre-
sentative currents of 100 pA to 10 mA, using R
C
the full 160 dB dynamic range. More optimal values may be used
for smaller subranges. A certain amount of experimental trial and
error may be necessary to select the optimum input network
component values for a given application.
Turning now to the noise performance of a translinear log amp,
the relationship between I
S
where S
For an input of 1 nA, S
ing a 20 kHz bandwidth at this current, the integrated noise
voltage is 70 µV rms. However, the calculation is not complete.
The basic scaling of the V
to 10 mV/dB, the noise predicted by Equation 14 must be multi-
plied by approximately 3.33. The additive noise effects associated
with the reference transistor, Q2, and the temperature compen-
sation circuitry must also be included. The final voltage noise
spectral density presented at the VLOG Pin varies inversely with
I
measured noise spectral density versus frequency at the VLOG
output, for the same nine-decade spaced values of I
Chip Enable
The AD8304 may be powered down by taking the PWDN Pin
to a high logic level. The residual supply current in the disabled
mode is typically 60 µA.
USING THE AD8304
The basic connections (Figure 3) include a 2.5:1 attenuator in
the feedback path around the buffer. This increases the basic slope
of 10 mV/dB at the VLOG Pin to 25 mV/dB at V
full dynamic range of 160 dB (80 dB optical), the output swing
PD
NSD
1
S
, but not as simple as square root. TPC
= 1000 pF. The values for R1 and C1 ensure stability over
NSD
, associated with the V
NSD
=
1.6
1.2
0.8
0.4
100p
0
14 7 .
is nV/Hz, I
I
Figure 2. Ideal Form of V
PD
1n
PD
10n
NSD
is expressed in microamps and T
PD
BE
evaluates to almost 0.5 µV/√Hz; assum-
100n
BE
and the voltage noise spectral density,
is approximately 3 mV/dB; translated
J
of Q1, evaluates to the following:
evaluates to 20 MHz/mA. There-
INPUT – A
1
PD
= 100 pA would be 2 kHz.
10
LOG
S
8 and 9 show the
100
vs. I
1
= 750 Ω and
PD
OUT
1m
PD
. For the
.
A
= 25°C.
10m
(14)
PD
.
–10–
is thus 4.0 V, which can be accommodated by the rail-to-rail
output stage when using the recommended 5 V supply.
The capacitor from VLOG to ground forms an optional single-
pole low-pass filter. Since the resistance at this pin is trimmed
to 5 kΩ, an accurate time constant can be realized. For ex-
ample, with C
3.2 kHz. Such filtering is useful in minimizing the output noise,
particularly when I
tive in reducing noise, and are discussed below. A capacitor
between VSUM and ground is essential for minimizing the
noise on this node. When the bias voltage at either VPDB or
VREF is not needed these pins should be left unconnected.
Slope and Intercept Adjustments
The choice of slope and intercept depends on the application.
The versatility of the AD8304 permits optimal choices to be
made in two common situations. First, it allows an input current
range of less than the full 160 dB to use the available voltage span
at the output. Second, it allows this output voltage range to be
optimally positioned to fit the input capacity of a subsequent
ADC. In special applications, very high slopes, such as 1 V/dec,
allow small subranges of I
The slope can be lowered without limit by the addition of a
shunt resistor, R
at this pin is trimmed to 5 kΩ, the accuracy of the modified
slope will depend on the external resistor. It is calculated using:
For example, using R
decade or 3.75 mV/dB. Table I provides a selection of suitable
values for R
NC = NO CONNECT
R1
750
V
10nF
C1
1nF
I
PD
Y
NC
Figure 3. Basic Connections (RA, RB, CFLT are
optional; R1 and C1 are the default values)
=
R
3
4
5
'
VPDB
VSUM
INPT
VSUM
V R
S
VNEG
Table I. Examples of Lowering the Slope
S
Y
+
R
3
5
15
and the resulting slopes.
5 Ω
VPS2
FLT
S
S
k
S
1
(k )
, from VLOG to ground. Since the resistance
PDB
= 10 nF, the –3 dB corner frequency is
10
PD
S
is small. Multipole filters are more effec-
= 3 kΩ, the slope is lowered to 75 mV per
~10k
PWDN
PD
COMPENSATION
TEMPERATURE
ACOM
BIAS
to be covered at high sensitivity.
2
14
V
75
100
150
Y
VPS1
0.5V
(mV/dec)
VREF
VOUT
12
5k
11
BFNG
VLOG
BFIN
13
7
8
9
V
VREF
200mV/DEC
P
V
500mV/DEC
REV. A
RA
15k
OUT
10k
CFLT
RB
(15)