AD8306AR Analog Devices Inc, AD8306AR Datasheet - Page 2

• Manufacturer Part Number: AD8306AR
• Description: Logarithmic Amplifier IC
• Manufacturer: Analog Devices Inc
• Type: Limiting-Logarithmic Amplifierr

Specifications of AD8306AR

• No. Of Amplifiers: 1
• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• Bandwidth: 400MHz
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Rohs Status: RoHS non-compliant
• Applications: Receiver Signal Strength Indication (RSSI)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Parameter
INPUT STAGE
LIMITING AMPLIFIER
LOGARITHMIC AMPLIFIER
POWER INTERFACES
TRANSISTOR COUNT
NOTES
1
2
3
4
Specifications subject to change without notice.
AD8306–SPECIFICATIONS
Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
The input level is specified in “dBV” since logarithmic amplifiers respond strictly to voltage, not power. 0 dBV corresponds to a sinusoidal single-frequency input of
Due to the extremely high Gain Bandwidth Product of the AD8306, the output of either LMHI or LMLO will be unstable for levels below –78 dBV (–65 dBm, re 50 ).
Standard deviation remains essentially constant over frequency. See Figures 13, 14, 16 and 17.
1 V rms. A power level of 0 dBm (1 mW) in a 50
can be converted into dBm by adding a fixed offset of +13 to the dBV rms value.
Maximum Input
Equivalent Power in 50
Noise Floor
Equivalent Power in 50
Input Resistance
Input Capacitance
DC Bias Voltage
Usable Frequency Range
At Limiter Output
Phase Variation at 100 MHz
Limiter Output Current
Versus Temperature
Input Range
Maximum Output Voltage
Rise/Fall Time (10%–90%)
Transfer Slope
Over Temperature
Intercept (Log Offset)
Over Temperature
Temperature Sensitivity
Linearity Error (Ripple)
Output Voltage
Minimum Load Resistance, R
Maximum Sink Current
Output Resistance
Small-Signal Bandwidth
Output Settling Time to 2%
Rise/Fall Time (10%–90%)
Supply Voltage, V
Quiescent Current
Over Temperature
Disable Current
Additional Bias for Limiter
Logic Level to Enable Power
Input Current when HI
Logic Level to Disable Power
3 dB Error Dynamic Range
3
4
2
S
4
L
Over Input Range –73 dBV to –3 dBV
Conditions
(Inputs INHI, INLO)
Differential Drive, p-p
Terminated in 52.3
Terminated 50
400 MHz Bandwidth
From INHI to INLO
From INHI to INLO
Either Input
(Outputs LMHI, LMLO)
R
Nominally 400 mV/R
–40 C
At Either LMHI or LMLO, wrt VPS2
R
(Output VLOG)
From Noise Floor to Maximum Input
f = 10 MHz
f = 100 MHz
–40 C < T
f = 10 MHz
f = 100 MHz
–40 C
Input from –80 dBV to +0 dBV
Input = –91 dBV, V
Input = +9 dBV, V
Input = –3 dBV, V
To Ground
Large Scale Input, +3 dBV, R
Large Scale Input, +3 dBV, R
Zero-Signal, LMDR Open
–40 C < T
–40 C < T
R
HI Condition, –40 C < T
3 V at ENBL, –40 C < T
LO Condition, –40 C < T
# of Transistors
LOAD
LOAD
LIM
= 400
termination corresponds to an input of 0.2236 V rms. Hence, in the special case of 50
= R
= 50 , 40
T
T
A
A
LIM
A
A
A
< +85 C
< +85 C
< +85 C
+85 C
+85 C
(See Text)
= 50 , to –10 dB Point
(V
S
Source
= +5 V, T
S
S
S
= +3 V
= +5 V
LIM
= +5 V, +2.7 V
R
R
IN
LIM
A
A
A
< +85 C
A
< +85 C
–2–
< +85 C
= +25 C, f = 10 MHz, unless otherwise noted)
L
L
400
50 , C
50 , C
L
L
100 pF
100 pF
Min
800
5
0
–78
1
19.5
19.3
–109.5
–111
40
0.75
2.7
13
11
2.7
–0.5
3.5
1
Typ
+9
+22
1.28
–78
1000
2.5
1.725
585
1
–0.008
1.25
0.6
100
20
19.6
20
–108
–108.4
–108
–0.009
0.34
2.34
2.10
50
1.0
0.3
3.5
120
73
5
16
16
0.01
2.0
40
1
207
4
2
0.4
termination, dBV values
Max
1200
400
10
+9
20.5
20.7
–106.5 dBV
–105
2.75
1.25
220
100
6.5
20
23
4
2.25
V
60
207
S
1
Units
V
dBV
dBm
nV/ Hz
dBm
pF
V
MHz
MHz
Degrees
mA
%/ C
dBV
V
ns
dB
mV/dB
mV/dB
mV/dB
dBV
dBV
dB/ C
dB
V
V
V
mA
MHz
ns
ns
V
mA
mA
mA
V
V
REV. A
A
A