AD8348ARUZ-REEL7 Analog Devices Inc, AD8348ARUZ-REEL7 Datasheet - Page 18

• Manufacturer Part Number: AD8348ARUZ-REEL7
• Description: IC,Quadrature Demodulator,BIPOLAR,TSSOP,28PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8348ARUZ-REEL7

• Function: Demodulator
• Lo Frequency: 100MHz ~ 2GHz
• Rf Frequency: 50MHz ~ 1GHz
• P1db: -22dBm
• Gain: 25.5dB
• Noise Figure: 10.75dB
• Current - Supply: 58mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8348
THEORY OF OPERATION
ENBL
VGA
The VGA is implemented using the patented X-AMP architecture.
The single-ended IF signal is attenuated in eight discrete 6 dB
steps by a passive R-2R ladder. Each discrete attenuated version
of the IF signal is applied to the input of a transconductance
stage. The current outputs of all transconductance stages are
summed together and drive a resistive load at the output of the
VGA. Gain control is achieved by smoothly turning on and
off the relevant transconductance stages with a temperature-
compensated interpolation circuit. This scheme allows the gain
to continuously vary over a 44 dB range with linear-in-decibel
gain control. This configuration also keeps the relative dynamic
range constant (for example, IIP3 − NF in dB) over the gain
setting; however, the absolute intermodulation intercepts and
noise figure vary directly with gain. The analog voltage VGIN
sets the gain. VGIN = 0.2 V is the maximum gain setting, and
VGIN = 1.2 V is the minimum voltage gain setting.
DOWNCONVERSION MIXERS
The output of the VGA drives two (I and Q) double-balanced
Gilbert cell downconversion mixers. Alternatively, driving the
ENVG pin low can disable the VGA, and the mixers can be
externally driven directly via the MXIP and MXIN ports. At
the input of the mixer, a degenerated differential pair performs
linear voltage-to-current conversions. The differential output
current feeds into the mixer core where it is downconverted by
the mixing action of the Gilbert cell. The phase splitter provides
quadrature LO signals that drive the LO ports of the in-phase
and quadrature mixers.
Buffers at the output of each mixer drive the IMXO and QMXO
pins. These linear, low output impedance buffers drive 40 Ω,
temperature-stable, passive resistors in series with each output
pin (IMXO and QMXO). This 40 Ω should be considered when
calculating the reverse termination if an external filter is inserted
between IMXO (QMXO) and IAIN (QAIN). The VCMO pin sets
the dc output level of the buffer. This can be set externally or
connected to the on-chip 1.0 V reference, VREF.
VGIN
IFIN
IFIP
15
11
10
17
CONTROL
BIAS
CELL
GAIN
VREF
14
MXIP
18
Figure 48. Functional Block Diagram
VREF
MXIN
19
ENVG
24
QXMO
IMXO
21
8
IOFS
QOFS
13
16
VCMO
SPLITTER
QAIN
IAIN
PHASE
23
DIVIDE
6
BY 2
VCMO
AD8348
QOPP QOPN
IOPP
25
4
IOPN
26
3
28
5
1
VCMO
LOIP
LOIN
Rev. A | Page 18 of 28
PHASE SPLITTER
Quadrature generation is achieved using a divide-by-2 frequency
divider. Unlike a polyphase filter that achieves quadrature over
a limited frequency range, the divide-by-2 approach maintains
quadrature over a broad frequency range and does not attenuate
the LO. The user, however, must provide an external signal XLO
that is twice the frequency of the desired LO frequency. XLO drives
the clock inputs of two flip-flops that divide down the frequency
by a factor of 2. The outputs of the two flip-flops are one-half
period of XLO out of phase. Equivalently, the outputs are one-
quarter period (90°) of the desired LO frequency out of phase.
Because the transitions on XLO define the phase difference at
the outputs, deviation from 50% duty cycle translates directly to
quadrature phase errors.
If the user generates XLO from a 1× frequency (f
frequency-doubling circuit (XLO = 2 × f
there is a 180° phase uncertainty between f
internal quadrature LO. The phase relationship between I and Q
LO, however, is always 90°.
I/Q BASEBAND AMPLIFIERS
Two (I and Q) fixed gain (20 dB), single-ended-to-differential
amplifiers are provided to amplify the demodulated signal
after off-chip filtering. The amplifiers use voltage feedback to
linearize the gain over the demodulation bandwidth. These
amplifiers can be used to maximize the dynamic range at the
input of an ADC following the AD8348.
The input to the baseband amplifiers, IAIN (QAIN), feeds into
the base of a bipolar transistor with an input impedance of
roughly 50 kΩ. The baseband amplifiers sense the single-ended
difference between IAIN (QAIN) and VCMO. IAIN (QAIN)
can be dc biased by terminating it with a shunt resistor to
VCMO, such as when an external filter is inserted between
IMXO (QMXO) and IAIN (QAIN). Alternatively, any dc
connection to IMXO (QXMO) can provide appropriate bias via
the offset-nulling loop.
ENABLE
A master biasing cell that can be disabled using the ENBL pin
controls the biasing for the chip. If the ENBL pin is held low,
the entire chip powers down to a low power sleep mode,
typically consuming 75 μA at 5 V.
BASEBAND OFFSET CANCELLATION
A low output current integrator senses the output voltage offset
at IOPP and IOPN (QOPP and QOPN) and injects a nulling
current into the signal path. The integration time constant of the
offset-nulling loop is set by Capacitor COFS from IOFS (QOFS) to
REF
REF
), fundamentally
and the AD8348
REF
) and a