AD9204BCPZ-40 Analog Devices Inc, AD9204BCPZ-40 Datasheet - Page 10

• Manufacturer Part Number: AD9204BCPZ-40
• Description: 10 Bit 40 Msps Dual Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9204BCPZ-40

• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 97.7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9204
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Description
Pin No.
0
1, 2
3
4, 5, 6, 7, 8, 9, 25, 26, 27,
29, 30, 31
10, 19, 28, 37
11 to 18, 20, 21
22
23
24
32 to 36, 38 to 42
43
44
45
46
47
48
Mnemonic
GND
CLK+, CLK−
SYNC
NC
DRVDD
D0B to D9B
ORB
DCOB
DCOA
D0A to D9A
ORA
SDIO/DCS
SCLK/DFS
CSB
OEB
PDWN
D0B (LSB)
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
DRVDD
SYNC
CLK+
CLK–
D1B
D2B
D3B
D4B
D5B
NC
NC
NC
NC
NC
NC
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Description
Exposed paddle is the only ground connection for the chip. Must be connected to PCB AGND.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Do Not Connect.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Digital Outputs. D9B = MSB.
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D9A = MSB.
Channel A Out-of-Range Digital Output.
SPI Data Input/Output (SDIO). Bidirectional SPI Data I/O in SPI mode. 30 kΩ internal pull-
down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode.
30 kΩ internal pull-up in non-SPI (DCS) mode.
SPI Clock (SCLK) Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal
pull-down.
DFS high = twos complement output.
DFS low = offset binary output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
Digital Input. Enable Channel A and Channel B digital outputs if low, three-state outputs if
high. 30 kΩ internal pull-down.
Digital Input. 30 kΩ internal pull-down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
PIN 1
INDICATOR
Figure 5. Pin Configuration
Rev. 0 | Page 10 of 36
(Not to Scale)
AD9204
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D9A (MSB)
D8A
D7A
D6A
D5A
DRVDD
D4A
D3A
D2A
D1A