AD9219-65EB Analog Devices Inc, AD9219-65EB Datasheet - Page 23

• Manufacturer Part Number: AD9219-65EB
• Description: Quad 10-bit 65 MSPS Serial LVDS ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9219-65EB

• Number Of Adc's: 4
• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 378mW @ 1.8 V
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9219
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9219.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs at www.analog.com.
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 57. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated by
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
100
A
× t
14 BITS
12 BITS
16 BITS
J
)
1000
Rev. D | Page 23 of 52
A
)
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9219 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
Figure 58. Supply Current vs. f
Figure 59. Supply Current vs. f
200
180
160
140
120
100
140
120
100
80
60
40
20
80
60
40
20
0
0
10
10
15
20
20
30
DRVDD CURRENT
ENCODE (MSPS)
AVDD CURRENT
ENCODE (MSPS)
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
TOTAL POWER
SAMPLE
SAMPLE
25
for f
for f
40
IN
IN
= 10.3 MHz, f
= 10.3 MHz, f
30
50
35
SAMPLE
SAMPLE
60
AD9219
= 40 MSPS
= 65 MSPS
40
390
370
350
330
310
290
270
250
360
340
320
300
280
260
240
220
200
180