AD9219ABCPZ-65 Analog Devices Inc, AD9219ABCPZ-65 Datasheet
AD9219ABCPZ-65
Specifications of AD9219ABCPZ-65
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AD9219ABCPZ-65 Summary of contents
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FEATURES 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB (to Nyquist) ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL ...
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AD9219 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications ...
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SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error ...
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AD9219 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz IN f ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 ...
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AD9219 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table Parameter Temp 3 CLOCK Maximum Clock Rate Full ...
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TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± ...
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AD9219 N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – FRAME t DATA LSB ...
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ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x ...
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AD9219 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVDD AVDD VIN – D VIN + D AVDD AVDD CLK– CLK+ AVDD AVDD DRGND DRVDD Table 7. Pin Function Descriptions Pin No. Mnemonic 0 AGND 10, 27, 32, ...
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Pin No. Mnemonic 33 VIN + A 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN − C Description ADC A ...
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AD9219 EQUIVALENT CIRCUITS VIN ± x Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V AND PDWN Rev Page ...
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AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page AD9219 6kΩ ...
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AD9219 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.4 MHz –20 –40 –60 –80 –100 –120 0 ...
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ENOB = 9.13 BITS –20 SFDR = 66.41dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with f = 190 MHz ENOB = 9.44 BITS –20 SFDR ...
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AD9219 100 10.3MHz 40MSPS SAMPLE p-p, SFDR –60 –50 –40 –30 ANALOG INPUT LEVEL (dBFS) Figure 27. SNR/SFDR vs. Analog Input Level ...
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AIN1 AND AIN2 = –7dBFS –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Two-Tone 32k FFT with MHz and f IN1 MSPS SAMPLE 0 AIN1 AND ...
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AD9219 –45.0 –45.5 –46.0 –46.5 –47.0 –47.5 –48 FREQUENCY (MHz) Figure 39. CMRR vs. Frequency, f SAMPLE 1.2 1.0 0.8 0.6 0.4 0 – – – CODE ...
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THEORY OF OPERATION The AD9219 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in ...
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AD9219 80 75 SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 44. SNR/SFDR vs. Common-Mode Voltage 2.4 MHz MSPS IN SAMPLE ...
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For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common- mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference ...
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AD9219 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9219 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins ...
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Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f due only to aperture jitter (t ) can be calculated by J SNR ...
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AD9219 By asserting the PDWN pin high, the AD9219 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the ...
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EYE: ALL BITS 500 0 –500 –1ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only ...
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AD9219 Two output clocks are provided to assist in capturing data from the AD9219. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the ...
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When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure ...
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AD9219 SCLK/DTP Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power- up. ...
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Internal Reference Operation A comparator within the AD9219 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 64), setting VREF to ...
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AD9219 SERIAL PORT INTERFACE (SPI) The AD9219 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and ...
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NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 68. SDIO Pin Loading ...
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AD9219 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), ...
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Table 16. Memory Map Register Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X Child ID [6:4] (identify device variants ...
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AD9219 Addr. (MSB) (Hex) Register Name Bit 7 Bit 6 14 output_mode LVDS ANSI-644 (default LVDS low power (IEEE1596.3 similar) 15 output_adjust output_phase user_patt1_lsb user_patt1_msb B15 ...
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Power and Ground Recommendations When connecting power to the AD9219 recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed ...
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AD9219 EVALUATION BOARD The AD9219 evaluation board provides all of the support cir- cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default AD8332 driver. The ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9219 Rev. A evaluation board. • POWER: Connect the switching power supply that is provided in the evaluation ...
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AD9219 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which ...
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P102 VGA INPUT CONNECTION DNP INH1 AIN CHANNEL A R101 P101 DNP AIN FB101 R103 R102 0Ω 64.9Ω AVDD_DUT VGA INPUT CONNECTION INH2 CHANNEL B R114 P103 DNP AIN R115 64.9Ω C115 P106 R130 0.1µF DNP 0Ω VGA INPUT CONNECTION ...
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AD9219 AVDD_DUT CW V– VIN_B 37 VIN_B 38 AVDD_DUT 39 40 VSENSE_DUT 41 VREF_DUT AVDD_DUT 45 AVDD_DUT 46 VIN_C 47 VIN_C 48 Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface 2 2 ...
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POPULATE L301-L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. R301 DNP C301 L301 DNP 0Ω C303 L305 DNP 0Ω R303 DNP C305 0.1µF R305 374Ω R307 R308 187Ω 187Ω R312 U301 10kΩ 25 R313 ENBV 26 10kΩ ENBL DNP ...
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AD9219 FILTER. YOUR DESIGN OR RESISTORS 0Ω WITH L401-L408 POPULATE CH_A CH_A CH_B CH_B POWER) DISABLE = (0–1V ENABLE DOWN POWER Figure 76. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued) SDO_CHA 0Ω R427 SDI_CHA ...
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Figure 77. Evaluation Board Schematic, Power Supply Inputs Rev Page AD9219 05726-019 GND GND 1 1 GND GND 1 1 ...
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AD9219 Figure 78. Evaluation Board Layout, Primary Side Rev Page ...
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Figure 79. Evaluation Board Layout, Ground Plane Rev Page AD9219 ...
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AD9219 Figure 80. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD9219 ...
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AD9219 Table 17. Evaluation Board Bill of Materials (BOM) Item Qty. Reference Designator 1 1 AD9219LFCSP_REVA 2 75 C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, ...
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Item Qty. Reference Designator 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 1 J201 to J204 23 1 J401 24 8 L501, L502, L503, L504, L505, ...
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AD9219 Item Qty. Reference Designator 37 4 R161, R162, R163, R164 38 3 R202, R203, R204 39 1 R222 40 1 R213 41 1 R229 42 2 R230, R319 43 1 R228 44 1 R320 45 8 R307, R308, R309, ...
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Item Qty. Reference Designator 59 1 U502 60 1 U201 61 1 U203 62 1 U202 63 1 U403 64 1 U404 65 1 U402 1 This BOM is RoHS compliant. Device Package Value IC SOT-223 ADP3339AKC-3.3 IC LFCSP, AD9219BCPZ-65, ...
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... ORDERING GUIDE Model 1 Temperature Range AD9219ABCPZ-40 −40°C to +85°C AD9219ABCPZRL7-40 −40°C to +85°C AD9219ABCPZ-65 −40°C to +85°C AD9219ABCPZRL7-65 −40°C to +85°C AD9219-65EBZ RoHS Compliant Part. ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...