AD9239-250KITZ Analog Devices Inc, AD9239-250KITZ Datasheet - Page 22

• Manufacturer Part Number: AD9239-250KITZ
• Description: Quad 12 Bit 250 MSPS Serial ADC-Evl Brd
• Manufacturer: Analog Devices Inc

Specifications of AD9239-250KITZ

• Number Of Adc's: 4
• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 1.25 Vpp
• Power (typ) @ Conditions: 1.526W @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9239
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9239
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (f
due only to aperture jitter (t
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9239.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note, the AN-756 Application
Note, and the Analog Dialogue article “Analog-to-Digital Converter
Clock Optimization: A Test Engineering Perspective” (Volume 42,
Number 2, February 2008) for more in-depth information about
jitter performance as it relates to ADCs (visit www.analog.com).
Power Dissipation
As shown in Figure 58 to Figure 60, the power dissipated by the
AD9239 is proportional to its clock rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the digital
output drivers.
SNR Degradation = 20 × log 10(1/2 × π × f
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
RMS CLOCK JITTER REQUIREMENT
Figure 57. Ideal SNR vs. Input Frequency and Jitter
ANALOG INPUT FREQUENCY (MHz)
10
J
) can be calculated by
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
100
A
× t
14 BITS
12 BITS
16 BITS
J
)
1000
Rev. B | Page 22 of 40
A
)
Figure 58. Supply Current vs. Encode for f
Figure 59. Supply Current vs. Encode for f
Figure 60. Supply Current vs. Encode for f
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0
50
50
50
70
70
70
90
90
110
90
110
POWER
I
ENCODE (MSPS)
ENCODE (MSPS)
ENCODE (MSPS)
DRVDD
130
I
AVDD
POWER
POWER
I
I
I
DRVDD
I
DRVDD
AVDD
AVDD
150
110
130
170
IN
IN
IN
150
= 84.3 MHz, f
= 84.3 MHz, f
= 84.3 MHz, f
130
190
170
210
150
SAMPLE
SAMPLE
SAMPLE
190
230
= 170 MSPS
= 210 MSPS
= 250 MSPS
170
250
210
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0