AD9246-105EBZ Analog Devices Inc, AD9246-105EBZ Datasheet - Page 27

• Manufacturer Part Number: AD9246-105EBZ
• Description: 1.8V 14Bit 105 MSPS ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9246-105EBZ

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 373mW @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9246-105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LAYOUT CONSIDERATIONS
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9246, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal).
If only a single 1.8 V supply is available, it is routed to AVDD
first, then tapped off and isolated with a ferrite bead or filter
choke with decoupling capacitors proceeding connection to
DRVDD. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These should
be located close to the point of entry at the PC board level and
close to the parts with minimal trace length.
A single PC board ground plane is sufficient when using the
AD9246. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9246. An
exposed, continuous copper plane on the PCB should mate to
the AD9246 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie
point between the ADC and PCB. See Figure 58 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.
Rev. A | Page 27 of 44
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 38.
RBIAS
The AD9246 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with
a low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low
ESR capacitor. In all reference configurations, REFT and REFB
are bypass points provided for reducing the noise contributed
by the internal reference buffer. It is recommended that an external
0.1 μF ceramic capacitor be placed across REFT/REFB. While
placement of this 0.1 μF capacitor is not required, the SNR
performance degrades by approximately 0.1 dB without it. All
reference decoupling capacitors should be placed as close to the
ADC as possible with minimal trace lengths.
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 58. Typical PCB Layout
AD9246